Brian A Kuns
age ~48
from Beaverton, OR
- Also known as:
-
- Brian Andrew Kuns
- Brian A Cuns
- Brian Kunz
- Phone and address:
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18131 Shady Meadow Ct, Beaverton, OR 97007
5032599993
Brian Kuns Phones & Addresses
- 18131 Shady Meadow Ct, Beaverton, OR 97007 • 5032599993
- 2172 Thorncroft Dr, Hillsboro, OR 97124
- 2192 Thorncroft Dr, Hillsboro, OR 97124
- 119 Quillen Ct, Stanford, CA 94305
- Seattle, WA
- Portland, OR
- Honolulu, HI
Work
-
Company:Intel corporationJul 2009
-
Position:Component debug engineer
Education
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Degree:Master of Science, Masters
-
School / High School:Stanford University1999 to 2000
-
Specialities:Electronics Engineering
Skills
Very Large Scale Integration • Java • Perl • Python • Silicon • Microprocessors • System on A Chip • Debugging • Computer Aided Design • Object Oriented Programming
Industries
Semiconductors
Resumes
Component Debug Engineer
view sourceLocation:
Beaverton, OR
Industry:
Semiconductors
Work:
Intel Corporation
Component Debug Engineer
Intel Corporation Jul 2000 - Jun 2009
Component Design Engineer
Component Debug Engineer
Intel Corporation Jul 2000 - Jun 2009
Component Design Engineer
Education:
Stanford University 1999 - 2000
Master of Science, Masters, Electronics Engineering Seattle Pacific University 1995 - 1999
Bachelors, Bachelor of Science, Electronics Engineering
Master of Science, Masters, Electronics Engineering Seattle Pacific University 1995 - 1999
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Very Large Scale Integration
Java
Perl
Python
Silicon
Microprocessors
System on A Chip
Debugging
Computer Aided Design
Object Oriented Programming
Java
Perl
Python
Silicon
Microprocessors
System on A Chip
Debugging
Computer Aided Design
Object Oriented Programming
Us Patents
-
Ultra Low Voltage, Low Leakage, High Density, Variation Tolerant Memory Bit Cells
view source -
US Patent:20090168509, Jul 2, 2009
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Filed:Dec 31, 2007
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Appl. No.:12/006288
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Inventors:Sapumal Wijeratne - Portland OR, US
Matthew W. Ernest - Hillsboro OR, US
Brian A. Kuns - Beaverton OR, US -
International Classification:G11C 11/40
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US Classification:365181
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Abstract:Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.
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