Brian E Larson

Address:

21245 Isotope Trl, Lakeville, MN 55044

Phone:

9523569087

VIN:

1FMCU9E79BKA16017

Make:

FORD

Model:

ESCAPE

Year:

2011

US Patent:

6504841, Jan 7, 2003

Filed:

Oct 26, 1999

Appl. No.:

09/426466

Inventors:

Brian Ralph Larson - Eagan MN
Charles Kryzak - Mendota Heights MN

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H04L 1250

US Classification:

370386, 3408255

Abstract:

Scalable Computer Interconnect (CSI) compliant multi-stage switching networks compactly electrically communicatively interconnect a large number N of electrically communicating devices, typically computers or memories, in three-dimensional space. The logic networks, including a preferred âlayered networkâ of U. S. Pat. No. 4,833,468, are (i) rotated, (ii) folded and (iii) squared per companion U. S. Pat. No. 6,301,247 so as to assume optimal topology. The topologically-optimized switching network logic is physically realized as (i) planar panels each mounting multi-chip modules, or tiles, each having logic switchpoints each realized by switch dice, plus vias through the tiles, plus pads upon both sides of the tiles, plus connective wiring layers upon the tile, connected by (ii) multi-conductor flexible flat printed circuit cables located between the adjacent panels. System peak performance is 24 teraflops/second.

US Patent:

D4142012, Sep 21, 1999

Filed:

Sep 29, 1998

Appl. No.:

D/094233

Inventors:

Brian Larson - Crystal Lake IL
Herbert Caderas - Lewisburg TN
Gary Keele - Normandy TN

Assignee:

Sanford Corporation - Bellwood IL

International Classification:

1906

US Classification:

D19 36

US Patent:

44981775, Feb 5, 1985

Filed:

Aug 30, 1982

Appl. No.:

6/412487

Inventors:

Brian R. Larson - Eagan MN

Assignee:

Sperry Corporation - New York NY

International Classification:

H03K 1332

US Classification:

371 52

Abstract:

An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln. sub. 2 (N/3)+1 bits width at level ln. sub. 2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2. sup. X+1. gtoreq. N. A final comparator stage based on exclusive OR gates and an OR gate(s) compares the X+1 signals representing the actual bit count with an equal number of binary encoded signals representing the then desired number M, M. ltoreq.

US Patent:

47232420, Feb 2, 1988

Filed:

Jun 27, 1986

Appl. No.:

6/879695

Inventors:

Brian R. Larson - Inver Grove Heights MN
Donald B. Bennett - Burnsville MN
Thomas O. Wolff - Fridley MN

Assignee:

Sperry Corporation - Blue Bell PA

International Classification:

G06F 1118

US Classification:

371 36

Abstract:

A digital system employing adaptive voting circuitry to improve its fault-tolerance receives an input data bit from each of a number of input data sources. The adaptive voting circuitry has a separate section for each of the input devices which has a weight register that stores an initial weight value which determines the voting strength of the associated input device. The weight values are multiplexed through to a voting circuit which also receives the input data bits. If an input data bit is a logic "1" the weight value of the input data device that supplied this "1" signal is added to the weight values of all other input data devices that supplied "1" data bits. If the data bit from a particular input device is a logic "0", then its weight is added to the weight values for other input data devices which supplied logic "0'". Accumulative voting then takes place via adders in the voting circuit which determines whether the correct output bit should be a logic "1" or a logic "0". After the correct output bit is obtained, it is compared with the input bits supplied by the different input data devices, and the stoned weight values associated with each of these are decremented if the input device supplied a data bit that did not conform to the correct output bit, or alternately they are incremented if it did.

US Patent:

62121790, Apr 3, 2001

Filed:

Feb 27, 1998

Appl. No.:

9/032534

Inventors:

Steven Allen Murphy - Apple Valley MN
Donald Bruce Bennett - Apple Valley MN
Brian Ralph Larson - Eagan MN

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H04L 1250

US Classification:

370370

Abstract:

An expandable network constructed from a plurality of identical network fabric cards which uses a plurality of selected row address bits to route connection paths between adjacent columns of interconnecting switches and a software algorithm for implementing a network of any whole number power of 2 rows or ports by assigning numbers of the network switches and attached nodes are described.

US Patent:

62157868, Apr 10, 2001

Filed:

Apr 6, 1998

Appl. No.:

9/055396

Inventors:

Brian Ralph Larson - Eagan MN
Steven Allen Murphy - Apple Valley MN

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H04L 1250

US Classification:

370386

Abstract:

Multi-stage switching networks may be constructed and expanded from small to very large networks that are contained within a compact physical volume. This is accomplished by replication of a pre-selected network module containing switches by a rotating, folding and squaring process that substantially reduces the length of connections between switches. This geometry allows very large networks by inductively combining smaller networks into larger networks. In networks constructed with this geometry, the length of the longest connections between switches is proportional to the square root of the number of ports provided by the network.

US Patent:

D368056, Mar 27, 1990

Filed:

Apr 3, 1987

Appl. No.:

7/034266

Inventors:

Brian F. Larson - Lake Zurich IL
Robert O'Neil - Glen Ellyn IL

Assignee:

Fellowes Manufacturing Co. - Itasca IL

US Classification:

D 6462

US Patent:

62032259, Mar 20, 2001

Filed:

Sep 29, 1998

Appl. No.:

9/162511

Inventors:

Rodney J. Baudino - Woodridge IL
Brian F. Larson - Crystal Lake IL

Assignee:

Sanford, L. P. - Bellwood IL

International Classification:

A46B 502

US Classification:

401 6

Abstract:

A writing implement comprising: a barrel; a compressible grip disposed over the barrel having an outer surface that includes at least two recessed portions, each recessed portion creating a concave depression running at least some portion of the length of the grip, each recessed portion having a plurality of ribs; and an air gap provided between the barrel and the grip.