Brian J O'Leary

US Patent:

54559316, Oct 3, 1995

Filed:

Nov 19, 1993

Appl. No.:

8/155178

Inventors:

Peter J. Camporese - Hopewell Junction NY
Patrick J. Meaney - Poughkeepsie NY
Brian J. O'Leary - Hyde Park NY
Richard F. Rizzolo - Red Hook NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 104

US Classification:

395550

Abstract:

A clock tuning system and method for a data processing system with enhanced timing failure diagnostics and unlayering capabilities. Both common and individual phase adjusting capabilities ensure programmable tuning of clock pulses distributed throughout a computer system, thereby facilitating isolation of timing margin failure to specific clock signals or enhancing system performance by shifting timing margin between logic paths. Both single-clock and dual-clock data processing are discussed, as well as clock tuning embodiments for each.