Brian S Reilly

US Patent:

61572322, Dec 5, 2000

Filed:

Mar 18, 1999

Appl. No.:

9/271825

Inventors:

Steven E. Hossner - Hillsboro OR
Brian F. Reilly - Hillsboro OR
Jeremy H. Smith - Beaverton OR

Assignee:

NEC Corporation - Tokyo

International Classification:

H03L 708

US Classification:

327159

Abstract:

A local clock system for generating a local clock signal whose frequency and phase are synchronized to the frequency and phase of an external input clock reference signal, wherein the output local clock signal is a non-integer multiple of the input clock reference signal. A numerically controlled generator generates the clock output signal, and the frequency and phase thereof are controlled by a digital tuning word input thereto. An input frequency divider divides the input clock reference signal by a first constant k. sub. 11 or a second constant k. sub. 22, and an output frequency divider for dividing the output signal by a first constant k. sub. 11 or a second constant k. sub. 21. A relay-phase detector receives output signals from the input frequency divider and the output frequency divider, and produces a 0 or a 1 output, which controls the input frequency divider to divide by k. sub. 12 or k. sub. 22 and controls the output frequency divider to divide by k. sub. 11 or k. sub.

US Patent:

53901800, Feb 14, 1995

Filed:

Feb 16, 1994

Appl. No.:

8/197767

Inventors:

Brian F. Reilly - Hillsboro OR

Assignee:

NEC America, Inc. - Melville NY

International Classification:

H04J 1408
H04L 708

US Classification:

370 84

Abstract:

A SONET/DS-N desynchronizer and method for receiving an incoming stream of SONET (Synchronous Optical NETwork) data, having a controller for controlling numerically controlled oscillator and clock circuit which provide a desynchronized clock for smoothly adapting the rate at which data is retrieved from a data buffer to the rate at which the incoming SONET data is stored in the data buffer. Pointer adjustments are processed separately from the SONET SPE payload frequency tracking. That is, the processing of pointers, which indicates a change in the phase of the SONET SPE payload, includes detecting negative or positive pointer hits by monitoring, for example, the H1, H2 bytes in the transport overhead, and advancing or retarding the phase over a predetermined period of time. On the other hand, the SONET SPE payload frequency tracking includes detecting positive or negative buffer offsets by monitoring the buffer offset signal OFFSET, and increasing or decreasing, respectively, the tuning word to compensate for the detected positive or negative buffer offset.

US Patent:

54732743, Dec 5, 1995

Filed:

Sep 14, 1992

Appl. No.:

7/944504

Inventors:

Brian F. Reilly - Hillsboro OR
Clifford A. Davidow - Portland OR

Assignee:

NEC America, Inc. - Melville NY

International Classification:

H03L 723

US Classification:

327159

Abstract:

A local clock system uses a numerically controlled oscillator referenced to a stable oscillator to generate local clock signals under microprocessor control. Two feedback loops provide inputs to the microprocessor for maintaining synchronization with the external clock reference; a frequency locked and a phase-locked loop. The relatively wide-band frequency-locked loop is used to acquire initial synchronization with the external clock reference when the external clock is restored after having been lost or is switched to a new source. The phase-locked loop has a narrow bandwidth and provides a large attenuation of any jitter on the incoming reference with a resultant low output jitter. The microprocessor provides a hold-over operation upon loss of the external clock reference and when the external reference is restored it slowly adjusts the output clock frequency to match that of the reference, limiting the rate of adjustment so as not to exceed a specified allowable jitter in the local clock output.