Brian J Reynolds

US Patent:

56279752, May 6, 1997

Filed:

Aug 2, 1994

Appl. No.:

8/284945

Inventors:

Christopher Bryant - Austin TX
Brian Reynolds - Round Rock TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1300

US Classification:

395307

Abstract:

An interbus buffer (18) coordinates data transfers between two different sized buses. The first bus (processor bus) allows data to be ordered according to either a big endian protocol or a "munged" little endian mode. The second bus (local bus) allows data to be ordered according to either a big endian protocol or a true little endian mode but does not define a transaction size. The disclosed interbus buffer coordinates interbus data transfers in spite of the variety of different transaction sizes and operating modes.

US Patent:

61638358, Dec 19, 2000

Filed:

Jul 6, 1998

Appl. No.:

9/110351

Inventors:

David William Todd - Austin TX
Michael Dean Snyder - Austin TX
Brian Keith Reynolds - Round Rock TX
Michael Julio Garcia - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1516

US Classification:

712 34

Abstract:

A method of transferring data between a slave device (20) in communication with a processor interface bus (34) where the processor interface bus is in communication with a master device (12) including receiving an address from the processor interface bus (34) where the address was provided by the master device (block 302). A first signal is asserted (blocks 318 and 324) on the processor interface bus (34) to indicate that the slave device (20) is servicing a data transfer transaction. A second signal is asserted (block 320) on the processor interface bus (34) to indicate whether data to be transferred using the processor interface bus (34) is to be stored in main memory (36) by a main memory controller (32) in communication with the processor interface bus (34). The data is transferred (block 326) between the slave device (20) and the processor interface bus (34).

US Patent:

62404792, May 29, 2001

Filed:

Jul 31, 1998

Appl. No.:

9/127459

Inventors:

Michael Dean Snyder - Austin TX
David William Todd - Austin TX
Brian Keith Reynolds - Round Rock TX
Michael Julio Garcia - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 13362

US Classification:

710113

Abstract:

A bus protocol for a split bus (50, 60) where each device (10, 20, 30) coupled to the bus has an age-based queue (12, 24, 34) of pending transactions. Queues are updated as transactions are executed. A central arbiter (40) has a copy of each device's queue (44). A priority transaction is determined from among all the queues in the arbiter. A data transaction index (DTI) is broadcast during the data tenure to all devices indicating the position in the queue of the next transaction. The index allows out-of-order data transfers without the provision of a static tag during the address tenure. Queues maintain a history of pending transactions. In one embodiment, each device receives a separate data bus grant (DBG), allowing a single provision of the index to both a source and a sink device.

US Patent:

20210224072, Jul 22, 2021

Filed:

Jan 22, 2020

Appl. No.:

16/749618

Inventors:

- Cupertino CA, US
Terence M. Potter - Austin TX, US
Anjana Rajendran - Austin TX, US
Jeffrey T. Brady - Orlando FL, US
Brian K. Reynolds - Austin TX, US
Jeffrey A. Lohman - Winter Park FL, US

International Classification:

G06F 9/38

Abstract:

Techniques are disclosed relating to context switching in a SIMD processor. In some embodiments, an apparatus includes pipeline circuitry configured to execute graphics instructions included in threads of a group of single-instruction multiple-data (SIMD) threads in a thread group. In some embodiments, context switch circuitry is configured to atomically: save, for the SIMD group, a program counter and information that indicates whether threads in the SIMD group are active using one or more context switch registers, set all threads to an active state for the SIMD group, and branch to handler code for the SIMD group. In some embodiments, the pipeline circuitry is configured to execute the handler code to save context information for the SIMD group and subsequently execute threads of another thread group. Disclosed techniques may allow instruction-level context switching even when some SIMD threads are non-active.

US Patent:

20190034166, Jan 31, 2019

Filed:

Sep 28, 2018

Appl. No.:

16/146147

Inventors:

- Cupertino CA, US
Terence M. Potter - Austin TX, US
Brian K. Reynolds - Austin TX, US
Justin Friesenhahn - Austin TX, US

International Classification:

G06F 7/505

Abstract:

Techniques are disclosed relating to performing arithmetic operations to generate values for different related threads. In some embodiments, the threads are graphics threads and the values are operand locations. In some embodiments, an apparatus includes circuitry configured to generate results for multiple threads by performing a plurality of arithmetic operations indicated by an instruction. In some embodiments, the instruction specifies: an input value that is common to the multiple threads and, for at least one of the multiple threads, a type value that indicates whether to generate a result for the thread by performing an arithmetic operation based on a first input that is a result of an arithmetic operation from another thread of the multiple threads or to generate a result for the thread using the input value that is common to the multiple threads. In some embodiments, the circuitry is configured to generate a result for the at least one of the multiple threads by selectively performing the arithmetic operation or using the input value that is common to the multiple threads based on the type value.

US Patent:

20180067748, Mar 8, 2018

Filed:

Sep 6, 2016

Appl. No.:

15/257386

Inventors:

- Cupertino CA, US
Brian K. Reynolds - Austin TX, US
Liang Xia - Austin TX, US
Terence M. Potter - Austin TX, US

International Classification:

G06F 9/38

Abstract:

Techniques are disclosed relating to clause-based execution of program instructions, which may be single-instruction multiple data (SIMD) computer instructions. In some embodiments, an apparatus includes execution circuitry configured to receive clauses of instructions and SIMD groups of input data to be operated on by the clauses. In some embodiments, the apparatus further includes one or more storage elements configured to store state information for clauses processed by the execution circuitry. In some embodiments, the apparatus further includes scheduling circuitry configured to send instructions of a first clause and corresponding input data for execution by the execution circuitry and indicate, prior to sending instruction and input data of a second clause to the execution circuitry for execution, whether the second clause and a first clause are assigned to operate on groups of input data corresponding to the same instruction stream. In some embodiments, the apparatus is configured to determine, based on the indication, whether to maintain as valid, for use by the second clause, stored state information for the first clause.

US Patent:

20150054837, Feb 26, 2015

Filed:

Aug 26, 2013

Appl. No.:

13/975520

Inventors:

- Cupertino CA, US
Brian K. Reynolds - Austin TX, US
Michael A. Geary - Round Rock TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06T 1/20

US Classification:

345506

Abstract:

Techniques are disclosed relating to predication. In one embodiment, a graphics processing unit is disclosed that includes a first set of architecturally-defined registers configured to store predication information. The graphics processing unit further includes a second set of registers configured to mirror the first set of registers and an execution pipeline configured to discontinue execution of an instruction sequence based on predication information in the second set of registers. In one embodiment, the second set of registers includes one or more registers proximal to an output of the execution pipeline. In some embodiments, the execution pipeline writes back a predicate value determined for a predicate writer to the second set of registers. The first set of architecturally-defined registers is then updated with the predicate value written back to the second set of registers. In some embodiments, the execution pipeline discontinues execution of the instruction sequence without stalling.

Address:

3112 Rippling Crk Ct, Austin, TX 78732

VIN:

5FNYF28547B033253

Make:

HONDA

Model:

PILOT

Year:

2007