Brian Michael Wade

US Patent:

20230040725, Feb 9, 2023

Filed:

Aug 4, 2021

Appl. No.:

17/394070

Inventors:

- Armonk NY, US
Peter Dana Driever - Poughkeepsie NY, US
Brian Keith Wade - Apalachin NY, US
Seth E. Lederer - Staatsburg NY, US

International Classification:

G06F 9/50
G06F 9/48
G06F 15/80

Abstract:

A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security parameters for information returned by the instruction which is topological information for mapping of the logical cores to the physical cores. The processor(s) obtains the topological information and utilizes an operating system to map the logical cores to the physical cores.