Bruce A Block

US Patent:

6706584, Mar 16, 2004

Filed:

Jun 29, 2001

Appl. No.:

09/895362

Inventors:

Richard Scott List - Beaverton OR
Bruce A. Block - Portland OR
Mark T. Bohr - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 218242

US Classification:

438239, 438250, 438253, 438612, 3613014, 3613062

Abstract:

A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.

US Patent:

6737699, May 18, 2004

Filed:

Jun 27, 2002

Appl. No.:

10/185798

Inventors:

Bruce A. Block - Portland OR
Richard Scott List - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01G 27108

US Classification:

257306, 257308, 257309

Abstract:

An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

US Patent:

6737728, May 18, 2004

Filed:

Oct 12, 2000

Appl. No.:

09/687906

Inventors:

Bruce A. Block - Portland OR
Richard Scott List - Beaverton OR
Ruitao Zhang - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27108

US Classification:

257532, 257296

Abstract:

On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. In one embodiment of the present invention, a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling.

US Patent:

6790780, Sep 14, 2004

Filed:

Sep 27, 2001

Appl. No.:

09/965972

Inventors:

Sarah E. Kim - Portland OR
R. Scott List - Beaverton OR
Bruce A. Block - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438692, 438694, 438696, 438700, 438702

Abstract:

A three dimensional capacitor fabricated as part of a dual damascene process is disclosed. The capacitor structure comprises two barrier metal layers separated by a high k dielectric and is formed in all the via and trench openings. The upper barrier layer and dielectric is selectively removed from those openings which will have ordinary vias and conductors, the other opening remains as capaitor.

US Patent:

6813431, Nov 2, 2004

Filed:

Feb 26, 2002

Appl. No.:

10/085474

Inventors:

Paul Davids - Portland OR
Bruce A. Block - Portland OR
Miriam R. Reshotko - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G02B 610

US Classification:

385129, 385 14, 385 27, 385 39, 385130, 385131, 385140, 257436

Abstract:

A waveguide includes a waveguide core that has a bottom surface and a top surface that defines an angle. The waveguide also includes a cladding layer adjacent to the bottom surface. The cladding layer has a thickness equal to or greater than an evanescent tail of a mode to be transmitted along the wave guide core.

US Patent:

6888716, May 3, 2005

Filed:

Jan 28, 2004

Appl. No.:

10/767559

Inventors:

Richard Scott List - Beaverton OR, US
Bruce A. Block - Portland OR, US
Mark T. Bohr - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01G004/228

US Classification:

3613062, 3023061, 3023014, 302307, 3023211, 3023215, 438240, 438250, 438253, 438256, 257532, 257295, 257296

Abstract:

A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.

US Patent:

6888974, May 3, 2005

Filed:

Apr 23, 2003

Appl. No.:

10/422345

Inventors:

Bruce A. Block - Portland OR, US
Brandon C. Barnett - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G02B006/26
G02B006/42

US Classification:

385 15, 385 1, 385 2, 385 3, 385 8, 385 14, 385 39, 385 40, 385 41, 385 42, 385 48, 385 88, 385 89

Abstract:

A microchip may include an optical signal routing system. The optical routing system may include a distribution waveguide coupled to a light source and signaling waveguides interconnecting source and destination locations. A directional coupler may be used to couple and modulate light from the distribution waveguide to a signaling waveguide at a source location. A photodetector may be used to convert light signals from the source location into electrical signals at the destination.

US Patent:

6888990, May 3, 2005

Filed:

Jun 24, 2003

Appl. No.:

10/606322

Inventors:

Bruce A. Block - Portland OR, US
Brandon Barnett - Beaverton OR, US
Paul Davids - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G02B006/00
G02B006/26
G02B006/36

US Classification:

385 50, 385 88, 385147

Abstract:

In an embodiment of the invention, an optical coupler couples light unidirectionally from integrated circuit package to an integrated circuit die. The package has a large waveguide with a waveguide core that has a low index of refraction. The die has a set of very small waveguide cores that have a high index of refraction relative to the index of refraction of the large waveguide core on the package. The waveguide cores with high index of refraction attract light from the waveguide core with the low index of refraction. No light is coupled back into the large waveguide core. Also, the optical mode of the large waveguide on the package is smaller than a subset of waveguide cores on the die. Thus, light is coupled from the package to the die without the waveguide cores having to be tightly aligned with each other.