Bruce W Cheney

US Patent:

51405407, Aug 18, 1992

Filed:

Jul 30, 1990

Appl. No.:

7/559795

Inventors:

Bruce W. Cheney - Sherwood OR
Donald C. Larson - Beaverton OR
Arnold M. Frisch - Portland OR

Assignee:

TriQuint Semiconductor, Inc. - Beaverton OR

International Classification:

G06F 102

US Classification:

364718

Abstract:

In a pipelined direct digital synthesis system (FIG. 3), new increment data (124) and/or phase modulation data (122) are input delay equalized by providing the data to a series of switch blocks (132), each switch block corresponding to a stage of the accumulator (124). Each switch block includes a multiplexer (132) for selecting among the new increment data, phase modulation data, and previously stored increment data, and includes a flip-flop circuit (134) for storing the selected increment data. A shift register (140) provides select signals (146) to each of the multiplexers. In operation, as a single bit propagates through the shift register, the select signals sequentially control the multiplexers to sequentially interleave blocks of selected increment data into respective accumulator stages in ascending order of binary significance. The invention thereby substantially reduces the input delay equalization circuitry necessary for coherent operation.