Bruce D Cory

US Patent:

20140282327, Sep 18, 2014

Filed:

Mar 14, 2013

Appl. No.:

13/830683

Inventors:

- Santa Clara CA, US
Bruce Cory - Aptos CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716112, 716136

Abstract:

A method for producing candidate fault circuitry in an integrated circuit (IC) is disclosed. The method comprises tracing back from at least one failing output of the IC to determine a corresponding fan-in cone for each failing output using simulation values obtained from a fault free simulation of a design of the IC. Further, it comprises determining a first set of suspect fault candidates for each failing output, wherein each suspect fault candidate potentially corresponds to a defective element in the IC. Next, it comprises tracing forward from each suspect in the first set to determine a second set of suspects, which is a narrower subset of the first set. Finally, it comprises identifying a failing block from the IC design, wherein the failing block comprises suspect fault candidates from the second set and can be simulated independently of the full design.