Bruce Mcrae Green

US Patent:

6867078, Mar 15, 2005

Filed:

Nov 19, 2003

Appl. No.:

10/716955

Inventors:

Bruce M. Green - Gilbert AZ, US
Olin L. Hartin - Phoenix AZ, US
Lawrence S. Klingbeil - Chandler AZ, US
Ellen Y. Lan - Chandler AZ, US
Hsin-Hua P. Li - Scottsdale AZ, US
Charles E. Weitzel - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L021/338
H01L021/3205

US Classification:

438167, 438172, 438175, 438182, 438285, 438590, 257183, 257192, 257194, 257195

Abstract:

A microwave field effect transistor () has a high conductivity gate () overlying a double heterojunction structure () that has an undoped channel layer (). The heterojunction structure overlies a substrate (). A recess layer that is a not intentionally doped (NID) layer () overlies the heterojunction structure and is formed with a predetermined thickness that minimizes impact ionization effects at an interface of a drain contact of source/drain ohmic contacts () and permits significantly higher voltage operation than previous step gate transistors. Another recess layer () is used to define a gate dimension. A Schottky gate opening () is formed within a step gate opening () to create a step gate structure. A channel layer () material of InGaAs is used to provide a region of electron confinement with improved transport characteristics that result in higher frequency of operation, higher power density and improved power-added efficiency.

US Patent:

7229903, Jun 12, 2007

Filed:

Aug 25, 2004

Appl. No.:

10/925855

Inventors:

Hsin-Hua P. Li - Scottsdale AZ, US
Bruce M. Green - Gilbert AZ, US
Olin L. Hartin - Phoenix AZ, US
Ellen Y. Lan - Chandler AZ, US
Charles E. Weitzel - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/28
H01L 21/44

US Classification:

438571, 438572, 438573, 438574, 438576

Abstract:

A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.

US Patent:

7253455, Aug 7, 2007

Filed:

Apr 5, 2005

Appl. No.:

11/100095

Inventors:

Bruce M. Green - Gilbert AZ, US
Olin L. Hartin - Chandler AZ, US
Ellen Y. Lan - Chandler AZ, US
Philip H. Li - Scottsdale AZ, US
Monte G. Miller - Phoenix AZ, US
Matthias Passlack - Chandler AZ, US
Marcus R. Ray - Tempe AZ, US
Charles E. Weitzel - Mesa AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 31/0328
H01L 31/0336
H01L 31/072
H01L 29/06

US Classification:

257194, 257 20, 257 24, 257192

Abstract:

In one embodiment, a semiconductor device () includes a buffer layer () formed over a substrate (). An AlGaAs layer () is formed over the buffer layer () and has a first doped region () formed therein. An InGaAs channel layer () is formed over the AlGaAs layer (). An AlGaAs layer () is formed over the InGaAs channel layer (), and the AlGaAs layer () has a second doped region formed therein. A GaAs layer () having a first recess is formed over the AlGaAs layer (). A control electrode () is formed over the AlGaAs layer (). A doped GaAs layer () is formed over the undoped GaAs layer () and on opposite sides of the control electrode () and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device () maintains linear operation over a wide temperature range.

US Patent:

7253486, Aug 7, 2007

Filed:

Jul 31, 2002

Appl. No.:

10/209746

Inventors:

Bruce M. Green - Gilbert AZ, US
Ellen Lan - Chandler AZ, US
Phillip Li - Scottsdale AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/76

US Classification:

257409, 257340, 257488, 257486, 257339, 257146, 257508, 257509, 438140, 438454

Abstract:

In one example embodiment, a transistor () is provided. The transistor () comprises a source (), a gate (), a drain (), and a field plate () located between the gate () and the drain (). The field plate () comprises a plurality of connection locations () and a plurality of electrical connectors () connecting said plurality of connection locations () to a potential.

US Patent:

7622322, Nov 24, 2009

Filed:

May 15, 2001

Appl. No.:

09/858337

Inventors:

William J. Schaff - Ithaca NY, US
Jeonghyun Hwang - Ithaca NY, US
Bruce M. Green - Gilbert AZ, US

Assignee:

Cornell Research Foundation, Inc. - Ithaca NY

International Classification:

H01L 21/00

US Classification:

438 94, 438172, 438191, 438235

Abstract:

A passivation layer of AlN is deposited on a GaN channel HFET using molecular beam epitaxy (MBE). Using MBE, many other surfaces may also be coated with AlN, including silicon devices, nitride devices, GaN based LEDs and lasers as well as other semiconductor systems. The deposition is performed at approximately 150 C. and uses alternating beams of aluminum and remote plasma RF nitrogen to produce an approximately 500 Å thick AlN layer.

US Patent:

7935620, May 3, 2011

Filed:

Dec 5, 2007

Appl. No.:

11/950820

Inventors:

Bruce M. Green - Gilbert AZ, US
Haldane S. Henry - Scottsdale AZ, US
Chun-Li Liu - Scottsdale AZ, US
Karen E. Moore - Phoenix AZ, US
Matthias Passlack - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/28

US Classification:

438570, 438572, 438575, 438580, 257E29041

Abstract:

Methods and apparatus are described for semiconductor devices. A method comprises providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor, and without removing the first mask, forming a Schottky contact of a first material on the exposed portion of the semiconductor, then removing the first mask, and using a further mask, forming a step-gate conductor of a second material electrically coupled to the Schottky contact and overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

US Patent:

8193591, Jun 5, 2012

Filed:

Apr 13, 2006

Appl. No.:

11/404714

Inventors:

Bruce M. Green - Gilbert AZ, US
Haldane S. Henry - Scottsdale AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

257401, 257797, 257618, 257626, 257622, 257E23179, 257E23132, 438401, 438462

Abstract:

Semiconductor devices () and methods (-) are provided with dual passivation layers (). A semiconductor layer () is formed on a substrate () and covered by a first passivation layer (PL-) (). PL- () and part () of the semiconductor layer () are etched to form a device mesa (). A second passivation layer (PL-) () is formed over PL- () and exposed edges () of the mesa (). Vias () are etched through PL- () and PL- () to the semiconductor layer () where source (), drain () and gate are to be formed. Conductors () are applied in the vias () for ohmic contacts for the source-drain () and a Schottky contact () for the gate. Interconnections () over the edges () of the mesa () couple other circuit elements. PL- () avoids adverse surface states () near the gate and PL- () insulates edges () of the mesa () from overlying interconnections () to avoid leakage currents (). An opaque alignment mark () is desirably formed at the same time as the device () to facilitate alignment when using transparent semiconductors ().

US Patent:

8304271, Nov 6, 2012

Filed:

May 20, 2009

Appl. No.:

12/469326

Inventors:

Jenn Hwa Huang - Chandler AZ, US
Bruce M. Green - Gilbert AZ, US

International Classification:

H01L 21/00

US Classification:

438 48, 257245, 257254, 257275, 257276, 257416, 257E27001, 257E27009, 257E27012, 257E27026, 438 6, 438 50, 438 53, 438167

Abstract:

A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.