Bruce E Newman

US Patent:

7535391, May 19, 2009

Filed:

Jan 7, 2008

Appl. No.:

11/969982

Inventors:

Bruce M. Newman - Gilbert AZ, US
Douglas A. Garrity - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03M 1/20

US Classification:

341131, 341155

Abstract:

An analog-to-digital converter (ADC) includes a multiplying digital-to-analog converter (MDAC) having a plurality of capacitors and a plurality of capacitor positions. The ADC generates a random number for a conversion cycle. The ADC configures each capacitor of the plurality of capacitors in a corresponding capacitor position of the plurality of capacitor positions based on the random number for the conversion cycle. The ADC converts, for the conversion cycle, a voltage of an analog signal to a digital value based on the capacitor configurations.

US Patent:

7898353, Mar 1, 2011

Filed:

May 15, 2009

Appl. No.:

12/466987

Inventors:

Merit Y. Hong - Chandler AZ, US
Bruce M. Newman - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03K 3/00
H03K 3/017
H03K 5/04
H03K 7/08

US Classification:

332109, 332112, 327176, 327237

Abstract:

A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals.

US Patent:

8022850, Sep 20, 2011

Filed:

Sep 25, 2009

Appl. No.:

12/566953

Inventors:

Bruce M. Newman - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03M 1/66

US Classification:

341144, 341143, 341155

Abstract:

Embodiments include DACs and methods for digital-to-analog conversion. A DAC includes an encoder and a plurality of DAC elements. The encoder maps each of a plurality of bits of a digital input value to one of the DAC elements, and produces a sign indication indicating whether a magnitude of the digital input value is above or below a threshold. Each DAC element produces a DAC element analog output signal that indicates whether a received sign indication and a received bit corresponds to a first state, a second state or a third state (e. g. , a zero, positive or negative state). In an embodiment, the DAC uses positive historic mapping information when the magnitude of the digital input value is above the threshold, and negative historic mapping information when the magnitude of the digital input value is below the threshold. DAC elements may be configurable into a Return-to-Zero or a Non-Return-to-Zero mode.

US Patent:

8415993, Apr 9, 2013

Filed:

Oct 26, 2011

Appl. No.:

13/281921

Inventors:

Bruce M. Newman - Gilbert AZ, US
Dean A. Badillo - Chandler AZ, US
Reimund Rebel - Maricopa AZ, US
Klaus Juergen Schoepf - Chandler AZ, US
Mohammad Asmani - Ladera Ranch CA, US

Assignee:

Sand 9, Inc. - Cambridge MA

International Classification:

H03L 7/00

US Classification:

327142, 143143, 143198, 143539

Abstract:

The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.