Bryan J Colvin

US Patent:

20040093569, May 13, 2004

Filed:

Nov 13, 2002

Appl. No.:

10/292104

Inventors:

Bryan Colvin - San Jose CA, US

International Classification:

G06F017/50

US Classification:

716/003000, 716/018000

Abstract:

This invention details an easy method for creating digital hardware timing systems from a text based hardware description language (HDL). Currently, chip designers must represent timing systems as state machines. Once completed, the state machine implementation does not visually resemble the original timing system. Often, a designer will document what the timing looks like by using a comment field; dashes and underscore characters make great looking timing diagrams when a fixed width font is used. A great deal of time may be saved by implementing the timing documentation directly into a state machine programmatically. Also saved is the time required to simulate and debug the state machine implementation. Design engineers are under extreme time pressures; an optimal implementation requires an extensive amount of time. What typically is implemented is the quickest possible solution. Current HDL synthesizers are constrained by what they are given, so the most optimal solution is rarely achieved. A program can be created to examine a plethora of different implementation possibilities and choose the one that creates the least amount of gates. Therefore, not only does the designer save a great deal of time, the design is also highly optimized.

US Patent:

20050198595, Sep 8, 2005

Filed:

May 5, 2005

Appl. No.:

11/121727

Inventors:

Bryan Colvin - San Jose CA, US

International Classification:

G06F017/50

US Classification:

716002000, 716003000, 716018000

Abstract:

This invention details a process whereby state assignments and decode logic of a state machine can be mapped to an optimized representation. Optimization may constitute a reduction of gates, an increase of speed, or a reduction of power utilization. Optimization is particularly important when implementing timing systems. A timing system is one of many possible configurations of a state machine. Design engineers are under extreme time pressures; an optimal implementation requires an extensive amount of time. What typically is implemented is the quickest possible solution. Current HDL synthesizers are constrained by what they are given, so the most optimal solution is rarely achieved. A program can be created to examine a plethora of different implementation possibilities and choose the one that creates the least amount of gates. Therefore, not only does the designer save a great deal of time, the design is also highly optimized.

US Patent:

55435785, Aug 6, 1996

Filed:

Sep 2, 1993

Appl. No.:

8/115958

Inventors:

Bryan J. Colvin - San Jose CA
Perry R. Cook - Palo Alto CA
Daniel Gochnauer - Saratoga CA

Assignee:

Mediavision, Inc. - Fremont CA

International Classification:

G10H 1057
G10H 112

US Classification:

84622

Abstract:

Synthesizer models for emulating musical instruments can be improved using an analysis model that compares the output signal of the model to a recording of a desired sound and derives a residual signal that can be used to correct the model. When the original model is a good one, the residual signal is small and takes much less memory to store than is required for a sampled sound.

US Patent:

54898650, Feb 6, 1996

Filed:

Feb 28, 1992

Appl. No.:

7/843492

Inventors:

Bryan J. Colvin - San Jose CA

Assignee:

Media Vision, Inc. - Fremont CA

International Classification:

H03K 3353

US Classification:

327198

Abstract:

A circuit is provided for filtering asynchronous metastability. The circuit includes two or more output lines that provide signals indicative of the assertion of control or data input signals at a plurality of input lines. Despite the simultaneous assertion of two or more input signals, the circuit prevents the simultaneous assertion of more than one output signal, thereby preventing adverse effects within a digital system connected to the circuit.

US Patent:

54689066, Nov 21, 1995

Filed:

Sep 2, 1993

Appl. No.:

8/116165

Inventors:

Bryan J. Colvin - San Jose CA
Perry R. Cook - Palo Alto CA

Assignee:

Media Vision, Inc. - Fremont CA

International Classification:

G10H 108
G10H 500

US Classification:

84625

Abstract:

Synthesizer models for emulating musical instruments are improved to take into account sympathetic string vibrations. One embodiment of the present invention scales an output signal from a sound synthesis model and uses the scaled signal as an input signal for a number of single-string emulations causing the single-string emulations to produce sound signals corresponding to sympathetic string vibrations. The output signals from the synthesis model and from all of the single-string emulations are added together. Another embodiment employs an octave's worth of single-string emulations to emulate the lower strings of an emulated instrument. Still another embodiment is a synthesizer which includes an input bus for accepting a sound signal, scaling means, a plurality of single-string emulations, and means for summing output signals from the string emulations. Embodiments preferably employ waveguide synthesis or the plucked string model to emulate single-strings.

US Patent:

55572278, Sep 17, 1996

Filed:

Apr 7, 1994

Appl. No.:

8/224442

Inventors:

Perry R. Cook - Palo Alto CA
Bryan J. Colvin - San Jose CA

Assignee:

Aureal Semiconductor - Fremont CA

International Classification:

G06F 7556

US Classification:

327346

Abstract:

Exponential and pseudo-exponential decay function values are generated by scaling a fractional decrease per sampling period by a previous decay function value and then subtracting the scaled fractional decrease from the previous decay function value. In one embodiment, a multiplier multiplies the fractional decrease by the previous decay function value and provides a product signal representing the scaled fractional decrease. An adder subtracts the scaled fractional decrease from the previous decay function value. In another embodiment, a shift block replaces the multiplier and approximates multiplication by a binary shift of the fractional decrease. The size of the shift is determined by the previous magnitude of the decay function as indicated by a priority encoder. Shifting generates a pseudo-exponential decay function which is suitable for music synthesis and can be generated quickly using less expensive hardware.

US Patent:

52452298, Sep 14, 1993

Filed:

Feb 28, 1992

Appl. No.:

7/843045

Inventors:

Bryan J. Colvin - San Jose CA

Assignee:

Media Vision - Fremont CA

International Classification:

G06G 716
H03K 522
H03F 100

US Classification:

307529

Abstract:

An anti-clipping mixer circuit is provided within an integrated circuit. The mixer circuit allows for the independent level control of each input signal, thereby allowing the optimization of the signal-to-noise ratio. A master level control is provided to limit the overall combined output signal to a level below the operational amplifier's maximum voltage level. A control circuit may be used to automatically adjust the input signal levels as well as the combined output signal level.

US Patent:

60411236, Mar 21, 2000

Filed:

Jul 1, 1996

Appl. No.:

8/673122

Inventors:

Bryan Colvin - San Jose CA

Assignee:

Allsoft Distributing Incorporated - San Jose CA

International Classification:

H04L 900

US Classification:

380 49

Abstract:

A system of secure communications between multiple parties. This system uses an index/secure key combination for each party. The index key never changes its value. A secured central router with access to a master database uses index keys to look up corresponding secure keys in the master database. The central router uses the secure keys to decrypt messages sent by parties and reencrypt the messages for the recipients and, thus, acts as a conduit for secure communications between parties.