Bryan R Kris

US Patent:

6525501, Feb 25, 2003

Filed:

May 26, 2000

Appl. No.:

09/580292

Inventors:

Bryan R. Kris - Chandler AZ
Cristian P. Masgras - Mesa AZ

Assignee:

Motorola - Schaumburg IL

International Classification:

G05B 1128

US Classification:

318599, 318807, 318811

Abstract:

The present invention is a method and apparatus for data communication between controllable devices, and more particularly, between a first programmable device ( ) and at least one second programmable device ( ) coupled to a processor. In one embodiment in accordance with the present invention, the second programmable device ( ) includes an addressable memory location and an output, and is adapted to receive data from a processor. In this embodiment, the first programmable device ( ) is programmed to decode at least one addressable memory location from the processor and enabled to transmit each address to each second programmable device ( ) in a first simultaneous write operation. The first programmable device ( ) then selects at least one of the second programmable devices ( ) to output a signal ( ) corresponding to the data in a second write operation.

US Patent:

6552567, Apr 22, 2003

Filed:

Sep 28, 2001

Appl. No.:

09/964664

Inventors:

Brian Boles - Mesa AZ
Richard Fischer - Mesa AZ
Sumit Mitra - Tempe AZ
Rodney Drake - Mesa AZ
Stephen A. Bowling - Chandler AZ
Bryan Kris - Chandler AZ
Steven Marsh - Phoenix AZ
Hassan Harb - Gilbert AZ

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H03K 190175

US Classification:

326 63, 327333

Abstract:

The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.

US Patent:

7126515, Oct 24, 2006

Filed:

Sep 27, 2005

Appl. No.:

11/236371

Inventors:

Bryan Kris - Phoenix AZ, US

Assignee:

Microchip Technology Inc. - Chandler AZ

International Classification:

H03M 1/00

US Classification:

341141, 341155

Abstract:

An analog-to-digital conversion apparatus for converting a plurality of analog input signals may include a plurality of analog input, a plurality of sample and hold circuits, one or more analog-to-digital converters (ADCs), a plurality of trigger selection circuits, and one or more analog multiplexers. The analog inputs may receive an analog input signals. The sample and hold circuits may include an input selectively coupled to at least one of the plurality of input and an output. The analog-to-digital converters (ADCs) may include an input and an output. The trigger selection circuits may selectively couple one of the inputs to one of the sample and hold circuits. The analog multiplexers may include a plurality of inputs selectively coupled to one or more of the sample and hold circuit outputs and an output coupled to one of the one or more analog-to-digital-converters.

US Patent:

7157890, Jan 2, 2007

Filed:

Mar 21, 2006

Appl. No.:

11/385374

Inventors:

Bryan Kris - Phoenix AZ, US

Assignee:

Microchip Technology Inc. - Chandler AZ

International Classification:

G05F 1/595

US Classification:

323272, 363 65

Abstract:

A plurality of power supply modules having their outputs coupled in parallel are controlled for load balancing purposes through a direct current bus having filtered pulse width modulation (PWM) signals representative of the power outputs of each of the plurality of power supply modules. A local PWM signal for each of the plurality of power supply modules is filtered to a DC voltage and used to compare with an average power required from each of the plurality of power supply modules.

US Patent:

7177166, Feb 13, 2007

Filed:

Aug 30, 2005

Appl. No.:

11/215622

Inventors:

Bryan Kris - Phoenix AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H02M 1/12
H02M 1/14

US Classification:

363 41, 323282, 323284, 323286

Abstract:

A switch mode power supply has pulse width modulation (PWM) frequency dithering of a PWM clock frequency. The PWM frequency dithering circuit may change the frequency of the PWM clock based upon each of a plurality of frequencies. A PWM time base circuit may comprise a period register containing a PWM period value, a comparator, and a PWM counter, wherein a PWM count value may be incremented in the PWM counter by the variable frequency PWM clock, the comparator may compare the PWM period value with the PWM count value and when the PWM period value and the PWM count value are substantially equal the PWM count value may be reset. The PWM frequency dithering circuit may comprise a roll counter, wherein the roll counter changes a roll count value each time the comparator resets the PWM count value in the PWM counter; a multiplexer having a plurality of inputs and an output, wherein the output is coupled to each one of the plurality of inputs of the multiplexer based upon the roll counter count value; and a plurality of frequency registers, each one of the plurality of frequency registers may be coupled to a respective one of the plurality of inputs of the multiplexer; wherein the output of the multiplexer may be coupled to a frequency control input of the variable frequency PWM clock such that frequency values stored in the plurality of frequency registers may be used in determining the variable frequency PWM clock frequency.

US Patent:

7376182, May 20, 2008

Filed:

Nov 10, 2004

Appl. No.:

10/986255

Inventors:

Bryan Kris - Phoenix AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H03K 7/08
H02M 1/12

US Classification:

375238, 363 41, 341 53

Abstract:

A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

US Patent:

7433404, Oct 7, 2008

Filed:

Mar 17, 2008

Appl. No.:

12/049402

Inventors:

Bryan Kris - Phoenix AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

H03K 7/08
H02M 1/12

US Classification:

375238, 363 41, 341 53

Abstract:

A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

US Patent:

7436207, Oct 14, 2008

Filed:

Feb 2, 2007

Appl. No.:

11/670771

Inventors:

J. Clark Rogers - Phoenix AZ, US
Bryan Kris - Phoenix AZ, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G06F 7/38

US Classification:

326 37, 326 38, 326 39, 326 41, 326 56, 341126, 341141

Abstract:

An integrated circuit device having at least one bond pad is coupled to a selectable plurality of input-output functionalities, e. g. , an oscillator input, an analog input, an analog output, a digital input and a digital output. These analog, digital and oscillator functionalities may selectably share the same integrated circuit package external connection.