Richard M. Gabrielson - Vestal NY Kevin W. McCauley - Greene NY Richard F. Rizzolo - Red Hook NY Bryan J. Robbins - Poughkeepsie NY Joseph M. Swenton - Owego NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 4, 714729, 714738, 714733, 714726
Abstract:
A method to improve the testability and analysis of a hierarchical semiconductor chip design formed from a plurality of macros, each macro identifying a particular portion of a semiconductor chip design. This method includes providing a first macro netlist that identifies a logical description of a first portion of the semiconductor chip design and performing RPT analysis on the first macro netlist. The method also includes providing a second macro netlist identifying a logical description of a second portion of the semiconductor chip design and performing an RPT analysis on the second macro netlist. The first macro netlist is combined with the second macro netlist and an RPT analysis is performed on the combination of the first and second macro netlists.
Method And Apparatus For Programmable Lbist Channel Weighting
Timothy J. Koprowski - Newburgh NY Mary P. Kusko - Hopewell Junction NY Lawrence K. Lange - Wappingers Falls NY Bryan J. Robbins - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 2900
US Classification:
714726, 714718, 324765, 365201, 365221
Abstract:
An exemplary embodiment of the invention is a built-in self-test (BIST) method and apparatus for testing the logic circuits on an integrated circuit. Random test pattern data is generated by a random pattern generator. A random resistant fault analysis (RRFA) program is used to determine the weighting requirements, on a per channel basis, for testing the logic circuits. The weighting requirements from the RRFA program are applied to the random test pattern data resulting in weighted test pattern data. The weighted test pattern data is then programmably applied to the scan chain.
Method And System For Determining Repeatable Yield Detractors Of Integrated Circuits
Richard F. Rizzolo - Red Hook NY Rocco E. DeStefano - Rhinebeck NY Joseph E. Eckelman - Hopewell Junction NY Thomas G. Foote - Milan NY Steven Michnowski - Wappingers Falls NY Franco Motika - Hopewell Junction NY Phillip J. Nigh - Williston VT Bryan J. Robbins - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3128
US Classification:
714732, 714738
Abstract:
An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.
Method And Apparatus For Facilitating Random Pattern Testing Of Logic Structures
Mary P. Kusko - Hopewell Junction NY William V. Huott - Holmes NY Bryan J. Robbins - Poughkeepsie NY Timothy Charest - West Hurley NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3128
US Classification:
714726, 714729, 714728, 714727
Abstract:
A method for preparing a logic structure for random pattern testing is disclosed. In an exemplary embodiment of the invention, the method includes configuring a select mechanism within a data scan chain, the select mechanism configured between a first register in the data scan chain and a second register. A parallel data path is routed within the scan chain, the parallel data path beginning from an input side of the first register, running through the select mechanism, and ending at an input side of the second register. Thus configured, the select mechanism is capable of switching a source path of input data to said second register from a normal data path to the parallel data path. When the parallel data path is selected as the source path of input data to the second register, data loaded into the second register matches data loaded into the first register.
Synchronous Bi-Directional Data Transfer Having Increased Bandwidth And Scan Test Features
Timothy G. McNamara - Fishkill NY, US Bryan J. Robbins - Poughkeepsie NY, US William R. Reohr - Bronx NY, US
International Classification:
H04J 15/00
US Classification:
370241, 714726
Abstract:
At least one swapper circuit is electrically connected to a bus between a plurality of entities sharing the bus. The swapper comprises a pair of series connected latches and a tristate circuits, one for each data direction, connected in parallel. The swapper acts as a revolving door, capturing data traveling from either side of the bus and shuffling the data to the other side without collision. A latch circuit is connected at either end of the bus for capturing data arriving from the other side. In addition, each of the drive entities is provided with a master/slave latched equipped with scan-in/scan-out ports, respectively, to enable testing of the circuit by allowing internal nodes of the circuit to be observed without requiring an external connection for each node accessed. In a VLSI arrangement, the scan-in/scan-out ports are connected together from a plurality of such circuits such that a variety of test patterns for various hardware configurations may be realized.
Automated Bist Test Pattern Sequence Generator Software System And Method
Donato O. Forlenza - Hopewell Junction NY, US Orazio P. Forlenza - Hopewell Junction NY, US William J. Hurley - Poughkeepsie NY, US Bryan J. Robbins - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28 G06F 11/00
US Classification:
714733, 714736
Abstract:
Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e. g. , logical BIST, array BIST, etc. ) and pattern structures are provided. Embodiments of the present invention store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.
Verification Of Array Built-In Self-Test (Abist) Design-For-Test/Design-For-Diagnostics (Dft/Dfd)
Donato Orazio Forlenza - Hopewell Junction NY, US Orazio Pasquale Forlenza - Hopewell Junction NY, US Bryan J. Robbins - Beavercreek OH, US Phong T. Tran - Highland NY, US
Assignee:
International Business Machines Corporation - Armonk NY
A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.
Method And Apparatus For Performing Logic Built-In Self-Testing Of An Integrated Circuit
Donato O. Forlenza - Hopewell Junction NY, US Orazio P. Forlenza - Hopewell Junction NY, US Bryan J. Robbins - Beavercreek OH, US Phong T. Tran - Highland NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28
US Classification:
714733, 714726, 714727, 714729, 714734
Abstract:
A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.
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Spotless Films - Owner, etc. Westwind Media / ABC Television - Telecine Assist Rushes - DI Supervisor, Colorist, Telecine Assist Day O Productions - Production Coordinator Lightstone Entertainment - Intern
Education:
Gnomon School of VFX - Compositing and Effects, Video Symphony - Avid Editing, Santa Monica Academy of Entertainment and Technology - General Production and Post-production
About:
Independent production and post-production professional, with experience on all sides of commercials, music videos, and currently focusing on the growing future of social media.
Bryan Robbins
Work:
Rackspace - Linux Administrator (2011)
Education:
Texas State University–San Marcos - Computer Science
Bryan Robbins
Work:
FINRA - Software tester (2012)
Tagline:
Software is essential to life; therefore, make it good.
Bryan Robbins, who runs the Greensburg Decatur County farmers market in Indiana, said it experienced a similar drop in attendance in recent weeks, so he started a new program for elderly customers who may be leery of the heat.
Date: Jul 31, 2012
Source: Google
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