Bryon G Conley

US Patent:

6516386, Feb 4, 2003

Filed:

Dec 31, 1997

Appl. No.:

09/002163

Inventors:

Roland Pang - Phoenix AZ
Gregory Mont Thornton - Aloha OR
Bryon George Conley - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711118, 711 3, 711203

Abstract:

A method for indexing a cache includes searching on a cache index using a partial physical address, the partial physical address including any bits of the virtual address which are untranslated between the virtual address and the physical address. The partial physical address is used to identify a block of the cache index sets that might contain an address of requested data. The identification is performed prior to translation of the virtual address to the physical address. Once identified, the block is read out into an auxiliary memory structure. After the full physical address becomes available, the block is multiplexed down to one set, and a compare is performed on the ways of the set to determine if the requested data is in the cache and, if so, which way the data is in. A device for achieving the method includes a cache index organized into two arrays, each having a number of sets and a number of ways. One of the arrays may used to store micro-tags for way prediction.

US Patent:

20030074537, Apr 17, 2003

Filed:

Nov 19, 2002

Appl. No.:

10/298961

Inventors:

Roland Pang - Phoenix AZ, US
Gregory Thornton - Aloha OR, US
Bryon Conley - Aloha OR, US

International Classification:

G06F012/00
G06F012/10

US Classification:

711/202000, 711/206000, 711/128000

Abstract:

A method for indexing a cache includes searching on a cache index using a partial physical address, the partial physical address including any bits of the virtual address which are untranslated between the virtual address and the physical address. The partial physical address is used to identify a block of the cache index sets that might contain an address of requested data. The identification is performed prior to translation of the virtual address to the physical address. Once identified, the block is read out into an auxiliary memory structure. After the full physical address becomes available, the block is multiplexed down to one set, and a compare is performed on the ways of the set to determine if the requested data is in the cache and, if so, which way the data is in. A device for achieving the method includes a cache index organized into two arrays, each having a number of sets and a number of ways. One of the arrays may used to store micro-tags for way prediction. In addition, the device includes an auxiliary memory structure for receiving and storing intermediate search results.

US Patent:

56358628, Jun 3, 1997

Filed:

Dec 29, 1995

Appl. No.:

8/580656

Inventors:

Jeffrey M. Abramson - Aloha OR
Bryon G. Conley - Hillsboro OR
Borislav Agapiev - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 140175

US Classification:

326105

Abstract:

A high-speed block id encoder circuit using dynamic logic includes a plurality of input signal lines received from a memory array and a plurality of output signal lines. A first portion of the encoder circuit pre-charges the plurality of output signal lines to a first state. A plurality of transistors coupled together in a single level receives the input signals and discharges the appropriate output signal lines to a second state based on the input signals. The signals produced on the output lines provide an encoded output identifying which one of the plurality of input signal lines is asserted.

US Patent:

57125783, Jan 27, 1998

Filed:

Dec 27, 1995

Appl. No.:

8/579095

Inventors:

Bryon G. Conley - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19177

US Classification:

326 39

Abstract:

A programmable logic array architecture having improved clock signal to output timing includes a logical AND plane and a logical OR plane. The logical AND plane generates a plurality of intermediary outputs responsive to the plurality of inputs. The logical OR plane then generates a plurality of outputs responsive to the plurality of intermediary outputs. The logical AND plane includes a plurality of semiconductors interconnected in a Type I dynamic logic configuration, and the logical OR plane includes a second plurality of semiconductors interconnected in a Type II dynamic logic configuration.

US Patent:

61382256, Oct 24, 2000

Filed:

Dec 24, 1997

Appl. No.:

8/998203

Inventors:

Michael Upton - Portland OR
Gregory Mont Thornton - Beaverton OR
Bryon Conley - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1210

US Classification:

711207

Abstract:

A memory system for providing rapid access to cached data includes a cache, a first TLB that stores address translation entries in a truncated form for fast access to data in the cache, and a second TLB that stores full address translation entries for accurate translation. The first TLB generates the tentative physical address quickly and initiates access to the cache using the tentative physical address. A way identified using the tentative physical address is read out of the cache and compared with a validated physical address provided by the second TLB. The initiated access is allowed to complete when the tentative and validated physical addresses match.