Byron Lee Williams

US Patent:

6376787, Apr 23, 2002

Filed:

Aug 24, 2000

Appl. No.:

09/648288

Inventors:

Wallace W. Martin - Richardson TX
Yu-Pei Chen - Plano TX
Byron Williams - Plano TX
Jose Melendez - Plano TX
Darius L. Crenshaw - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01H 5700

US Classification:

200181, 29622, 200600, 333262

Abstract:

A Micro Electro-Mechanical System (MEMS) switch ( ) having a bottom electrode ( ) formed over a substrate ( ) and a thin protective cap layer ( ) disposed over the bottom electrode ( ). A dielectric material ( ) is disposed over the protective cap layer ( ) and a pull-down electrode ( ) is formed over the spacer ( ) and the dielectric material ( ). The protective cap layer ( ) prevents the oxidation of the bottom electrode ( ). The thin protective cap layer ( ) comprises a metal having an associated oxide with a high dielectric constant. A portion ( ) of the thin protective cap layer ( ) may oxidize during the formation of the dielectric material ( ), increasing the capacitance of the dielectric stack ( ).

US Patent:

6525396, Feb 25, 2003

Filed:

Apr 17, 2001

Appl. No.:

09/836519

Inventors:

Jose L. Melendez - Plano TX
Byron Williams - Dallas TX
Yu-Pei Chen - Plano TX
Darius Crenshaw - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257528, 257415, 257418, 257532, 438 50, 438 53

Abstract:

The present invention provides an apparatus and method of selecting a unique combination of materials and dimensions for fabrication of a micro-electromechanical switch for improved RF switch performance. An electrode material is selected which exhibits a resistivity resulting in improved insertion loss for a predetermined switching speed, a dielectric material is selected which exhibits a permittivity resulting in improved isolation, and an airgap thickness is selected resulting in a pull-down voltage approximately equal to a supply voltage of the micro-electromechanical switch in which the isolation and predetermined switching speed are also functions of the airgap thickness.

US Patent:

6635919, Oct 21, 2003

Filed:

Aug 17, 2000

Appl. No.:

09/640410

Inventors:

Jose L. Melendez - Plano TX
Byron Williams - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27108

US Classification:

257312, 257595, 257600, 438 50, 438 52, 438 53, 200181, 200600

Abstract:

A Micro Electro-Mechanical System (MEMS) varactor ( ) having a bottom electrode ( ) formed over a substrate ( ) and a dielectric material ( ) disposed over the bottom electrode ( ). A pull-down electrode ( ) is formed over spacer ( ) and the dielectric material ( ). The MEMS varactor ( ) is adapted to operate in a stiction mode, with at least a portion of pull-down electrode ( ) in contact with dielectric material ( ). The MEMS varactor ( ) has a high Q, large tuning range, and high sensitivity.

US Patent:

7250334, Jul 31, 2007

Filed:

Jul 31, 2004

Appl. No.:

10/909648

Inventors:

Darius L. Crenshaw - Allen TX, US
Byron L. Williams - Plano TX, US
Alwin Tsao - Garland TX, US
Hisashi Shichijo - Plano TX, US
Satyavolu S. Papa Rao - Garland TX, US
Kenneth D. Brennan - Plano TX, US
Steven A. Lytle - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8242

US Classification:

438239, 438250, 438251, 438240, 257E21, 257351

Abstract:

A method () of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer () is formed against an edge () of a layer of bottom electrode/copper diffusion barrier material (), an edge () of a layer of capacitor dielectric material () and at least some of an edge () of a layer of top electrode material. The sidewall spacer () is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material () mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

US Patent:

7436281, Oct 14, 2008

Filed:

Jul 30, 2004

Appl. No.:

10/909046

Inventors:

Kenneth D. Brennan - Plano TX, US
Satyavolu S. Papa Rao - Garland TX, US
Byron Williams - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01F 5/00

US Classification:

336200

Abstract:

An inductor structure () formed in an integrated circuit () is disclosed, and includes a first isolation layer () and a first core plate () disposed over or within the first isolation layer (). The first core plate () includes a plurality of electrically coupled conductive traces composed of a conductive ferromagnetic material layer. A second isolation layer () overlies the first isolation layer and an inductor coil () composed of a conductive material layer () is formed within the second isolation layer (). Another core plate may be formed over the coil. The one or more core plates increase an inductance (L) of the inductor coil ().

US Patent:

7541275, Jun 2, 2009

Filed:

Apr 21, 2004

Appl. No.:

10/828592

Inventors:

Betty Shu Mercer - Plano TX, US
Erika Leigh Shoemaker - Richardson TX, US
Byron Lovell Williams - Plano TX, US
Laurinda W. Ng - Plano TX, US
Alec J. Morton - Plano TX, US
C. Matthew Thompson - Highland Village TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44

US Classification:

438614, 257737, 257E2302, 257E21477

Abstract:

The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (), among other elements, includes a surface conductive lead () located in an opening formed within a protective overcoat (), and a barrier layer () located between the protective overcoat () and the surface conductive lead (), a portion of the barrier layer () forming a skirt () that extends outside a footprint of the surface conductive lead ().

US Patent:

7670920, Mar 2, 2010

Filed:

Apr 9, 2007

Appl. No.:

11/697962

Inventors:

Byron Lovell Williams - Plano TX, US
C. Matthew Thompson - Highland Village TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27/108
H01L 29/94

US Classification:

438396, 257296, 257E2109, 257E29345

Abstract:

An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of polysilicon and depositing a second layer of polysilicon over the layer of dielectric. The method further includes implanting an equivalent concentration of implant in both the first layer of polysilicon into the second layer of polysilicon.

US Patent:

7902033, Mar 8, 2011

Filed:

Feb 12, 2008

Appl. No.:

12/029798

Inventors:

Byron Lovell Williams - Plano TX, US
Betty Mercer - Plano TX, US
Scott Montgomery - Rowlett TX, US
Binghua Hu - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/20

US Classification:

438393, 257532, 257E21008

Abstract:

An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.