Camila Jaramillo

US Patent:

20190043591, Feb 7, 2019

Filed:

Dec 8, 2017

Appl. No.:

15/836124

Inventors:

RICHARD FASTOW - Cupertino CA, US
XIN SUN - Fremont CA, US
UDAY CHANDRASEKHAR - Santa Clara CA, US
KRISHNA K. PARAT - Palo Alto CA, US
CAMILA JARAMILLO - San Jose CA, US
PURVAL S. SULE - Folsom CA, US
ALIASGAR S. MADRASWALA - Folsom CA, US

International Classification:

G11C 16/28
G11C 16/16
G11C 11/4074
G11C 16/34

Abstract:

A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.

US Patent:

20170285969, Oct 5, 2017

Filed:

Mar 30, 2016

Appl. No.:

15/085291

Inventors:

- Santa Clara CA, US
Yogesh B. Wakchaure - Folsom CA, US
Camila Jaramillo - San Jose CA, US
Trupti Bemalkhedkar - Folsom CA, US

International Classification:

G06F 3/06
G11C 16/22

Abstract:

A disclosed example to use an erase-suspend feature with a memory device includes sending, by a memory host controller, an erase-suspend enable setting and an erase segment duration value to the memory device. The erase-suspend enable setting is to cause the memory device to perform an erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments. The erase segment duration value is to specify a length of time for the erase segments. The memory host controller initiates an erase operation to be performed at the memory device. When the erase operation is suspended, the memory host controller initiates a second memory operation to be performed at the memory device. After the memory host controller determines that the second memory operation is complete, the memory host controller initiates resumption of the erase operation.