Carl Stuart Dobbs

US Patent:

20120137119, May 31, 2012

Filed:

Oct 14, 2011

Appl. No.:

13/274138

Inventors:

Michael B. Doerr - Dripping Springs TX, US
Carl S. Dobbs - Austin TX, US
Michael B. Solka - Austin TX, US
Michael R. Trocino - Austin TX, US
David A. Gibson - Austin TX, US

International Classification:

G06F 9/00

US Classification:

713100

Abstract:

Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.

US Patent:

20130343450, Dec 26, 2013

Filed:

Jun 11, 2013

Appl. No.:

13/915499

Inventors:

Michael B. Doerr - Dripping Springs TX, US
Carl S. Dobbs - Austin TX, US
Michael W. Bruns - Portland OR, US

International Classification:

H04N 7/26

US Classification:

37524003, 37524002

Abstract:

A split architecture for encoding a video stream. A source encoder may encode a video content stream to obtain an encoded bitstream and a side information stream. The side information stream includes information characterizing rate and/or distortion estimation functions per block of the video content stream. Also, a different set of estimation functions may be included per coding mode. The encoded bitstream and side information stream may be received by a video transcoder, which transcodes the encoded bitstream to a client-requested picture resolution, according to a client-requested video format and bit rate. The side information stream allows the transcoder to efficient and compactly perform rate control for its output bitstream, which is transmitted to the client device. This split architecture may be especially useful to operators of content delivery networks.

US Patent:

56300484, May 13, 1997

Filed:

May 19, 1994

Appl. No.:

8/246058

Inventors:

Leslie T. La Joie - Austin TX
Eugene M. Miller - Austin TX
Carl S. Dobbs - Austin TX
Michael B. Solka - Austin TX

International Classification:

G06F 1134

US Classification:

39518301

Abstract:

A monitoring system is coupled to an external computer system by an interface between a data bus internal to the monitoring system and a target bus within the external computer system. Data captured by the monitoring system from the external computer system is provided in parallel to a triggering circuit and to a buffer for temporary storage, The triggering circuit identifies the occurrence of a transaction on the bus of the external computer system and generates a signal to mark a captured data block within the buffer as being characteristic of the triggering transaction. The captured data block is compared with predetermined sets of known transaction data to determine if the captured data block is consistent with the normal operation of the external computer system. A second monitoring facility is provided to perform boundary scan testing on the external computer system.

US Patent:

51736179, Dec 22, 1992

Filed:

Aug 10, 1989

Appl. No.:

7/391689

Inventors:

Mitchell Alsup - Dripping Springs TX
Carl S. Dobbs - Austin TX
Yung Wu - Austin TX
Claude Moughanni - Austin TX
Elie I. Haddad - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 513
H03K 522

US Classification:

307269

Abstract:

A digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tapped output of the delay line goes through a two phase generator which in turn feeds back to the PD for comparison with the reference clock. This process is repeated until phase locking is obtained.

US Patent:

59335947, Aug 3, 1999

Filed:

Apr 23, 1997

Appl. No.:

8/838959

Inventors:

Leslie T. La Joie - Austin TX
Eugene M. Miller - Austin TX
Carl S. Dobbs - Austin TX
Michael B. Solka - Austin TX

International Classification:

G06F 1100

US Classification:

39518301

Abstract:

A monitoring system is coupled to an external computer system by an interface between a data bus internal to the monitoring system and a target bus within the external computer system. Data captured by the monitoring system from the external computer system is provided in parallel to a triggering circuit and to a buffer for temporary storage. The triggering circuit identifies the occurrence of a transaction on the bus of the external computer system and generates a signal to mark a captured data block within the buffer as being characteristic of the triggering transaction. The captured data block is compared with predetermined sets of known transaction data to determine if the captured data block is consistent with the normal operation of the external computer system. A second monitoring facility is provided to perform boundary scan testing on the external computer system.

US Patent:

20210208895, Jul 8, 2021

Filed:

Mar 16, 2021

Appl. No.:

17/203205

Inventors:

- Austin TX, US
Carl S. Dobbs - Austin TX, US
Michael B. Solka - Austin TX, US
Michael R. Trocino - Austin TX, US
Kenneth R. Faulkner - Austin TX, US
Keith M. Bindloss - Irvine CA, US
Sumeer Arya - Austin TX, US
John Mark Beardslee - Menlo Park CA, US
David A. Gibson - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30
G06F 12/02

Abstract:

Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.

US Patent:

20200319880, Oct 8, 2020

Filed:

Jun 22, 2020

Appl. No.:

16/907715

Inventors:

- Austin TX, US
Carl S. Dobbs - Austin TX, US
Evgeny Mezhibovsky - Waterloo, CA
Zahir Raza - Waterloo, CA
Kevin A. Shelby - Austin TX, US

International Classification:

G06F 9/30
G06F 17/18
G06F 9/38

Abstract:

Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.

US Patent:

20200302090, Sep 24, 2020

Filed:

Jun 10, 2020

Appl. No.:

16/897564

Inventors:

- Austin TX, US
Carl S. Dobbs - Austin TX, US
Michael B. Solka - Austin TX, US
Michael R. Trocino - Austin TX, US
David A. Gibson - Austin TX, US

International Classification:

G06F 21/71
G06F 15/163
G06F 15/76
G06F 15/167
G06F 15/173
G06F 9/4401
G06F 15/177
G06F 21/57

Abstract:

Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.