Carl F Semmelhaack

US Patent:

40074390, Feb 8, 1977

Filed:

Aug 18, 1975

Appl. No.:

5/605251

Inventors:

Carl Frederick Semmelhaack - West Chester PA
Mark Camillo Divecchio - Phoenixville PA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G06F 702

US Classification:

3401462

Abstract:

In a large parallel processing environment including a plurality of active registers storing either normalized floating point or integer data a high/low register selection circuit identifies selectively the register or registers storing either the highest or lowest numerical data value. The numerical data in each active register is first converted into a pure binary magnitude pattern having the same relative value as the original numerical data for a select high register search, and the inverse relative value for a select low register search. Thereafter, the binary patterns from all active registers are processed together two bits at a time through an OR network with the OR network output functioning to deactivate all registers having an OR'ed two bit pattern less than the OR network output value. The deactivating process is continued two bits at a time until either only one register remains active or all bits have been processed two bits at a time through the OR network.

US Patent:

40385388, Jul 26, 1977

Filed:

May 12, 1976

Appl. No.:

5/685615

Inventors:

Carl Frederick Semmelhaack - West Chester PA
Mark Camillo DiVecchio - Phoenixville PA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G06F 500

US Classification:

235154

Abstract:

In a data processing system having a plurality of storage units, each unit therein storing in integer or normalized floating point format, an exponent sign bit, an exponent field, an integer/fraction sign bit, and an integer/fraction field, a converter transforms the stored data into pure binary values of selectively the same or the inverse relative order. To convert into the same relative order, the exponent sign bit is complemented if the integer/fraction sign bit is a logical zero and the exponent is complemented if otherwise. Thereafter, the integer/fraction bit is complemented. To convert into the inverse relative order, the exponent sign bit is complemented if the integer/fraction sign bit is a logical one and the exponent field is complemented if otherwise. Also, the integer/fraction field is complemented.