Carlos Rafael Paz

US Patent:

59663189, Oct 12, 1999

Filed:

Dec 17, 1996

Appl. No.:

8/768256

Inventors:

O. Glenn Ramer - Los Angeles CA
John J. Drab - Santa Barbara CA
Larry D. McMillan - Colorado Springs CO
Carlos A. Paz de Araujo - Colorado Springs CO

Assignee:

Raytheon Company - Lexington MA

International Classification:

G11C 1122

US Classification:

365145

Abstract:

A memory includes a bitline data signal input (24), at least one memory unit (20), a writing circuit (128) which writes a polarization state into each memory unit (20) responsive to the bitline data signal input, and a sensing circuit (130) that senses a polarization state of each memory unit (20). Each memory unit (20) includes a ferroelectric capacitor (22) and a buffer amplifier (26) in electrical series relationship with the ferroelectric capacitor (22) and the bitline data signal input (24). The buffer amplifier (26) capacitively isolates the ferroelectric capacitor (22) from the bitline data signal input (24) so that the ferroelectric capacitor (22) may be made smaller in size than would otherwise be the case.