Carol O Namba from 538 Diamond Pl, Walnut, CA 91789, age 68, Phone: 6269125854

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High Electron Mobility Transistor Having Self-Aligned Miniature Field Mitigating Plate On A Protective Dielectric Layer
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US Patent:

7750370, Jul 6, 2010
Filed:

Dec 20, 2007
Appl. No.:

12/003098
Inventors:

Ioulia Smorchkova - Lakewood CA, US
Robert Coffie - Camarillo CA, US
Ben Heying - Fullerton CA, US
Carol Namba - Walnut CA, US
Po-Hsin Liu - Anaheim CA, US
Boris Hikin - Los Angeles CA, US
Assignee:

Northrop Grumman Space & Mission Systems Corp. - Los Angeles CA
International Classification:

H01L 29/778
H01L 21/338
US Classification:

257194, 257201, 257E29246
Abstract:

A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

High Electron Mobility Transistor Semiconductor Device Having Field Mitigating Plate And Fabrication Method Thereof
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US Patent:

7800132, Sep 21, 2010
Filed:

Oct 25, 2007
Appl. No.:

11/976590
Inventors:

Ioulia Smorchkova - Lakewood CA, US
Carol Namba - Walnut CA, US
Po-Hsin Liu - Anaheim CA, US
Robert Coffie - Camarillo CA, US
Roger Tsai - Torrance CA, US
Assignee:

Northrop Grumman Systems Corporation - Los Angeles CA
International Classification:

H01L 29/778
US Classification:

257194, 257192, 257E29246, 257E21403, 438172
Abstract:

A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.

Method And Apparatus For Detecting And Adjusting Substrate Height
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US Patent:

7800766, Sep 21, 2010
Filed:

Sep 21, 2007
Appl. No.:

11/859501
Inventors:

Carol Osaka Namba - Walnut CA, US
Po-Hsin Liu - Anaheim CA, US
Ioulia Smorchkova - Lakewood CA, US
Mike Wojtowicz - Long Beach CA, US
Rob Coffie - Camarillo CA, US
Assignee:

Northrop Grumman Space & Mission Systems Corp. - Los Angeles CA
International Classification:

G01B 11/14
H01J 37/304
US Classification:

356614, 356620, 2504911
Abstract:

A method and apparatus for detecting the height of non-flat and transparent substrates using one or more reflectors patterned on the surface of the substrate and adjusting the position of the substrate in its holder based on measurement of the height of the reflectors in comparison to a calibration marker on the holder and using appropriate spacers with appropriate thickness to adjust the placement of the substrate at various locations to place the greatest portion of the substrate in an optimal focal range of the lithography system.

Method Of Forming A High Electron Mobility Transistor Hemt, Utilizing Self-Aligned Miniature Field Mitigating Plate And Protective Dielectric Layer
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US Patent:

7897446, Mar 1, 2011
Filed:

Mar 25, 2010
Appl. No.:

12/659910
Inventors:

Ioulia Smorchkova - Lakewood CA, US
Robert Coffie - Camarillo CA, US
Ben Heying - Fullerton CA, US
Carol Namba - Walnut CA, US
Po-Hsin Liu - Anaheim CA, US
Boris Hikin - Los Angeles CA, US
Assignee:

Northrop Grumman Systems Corporation - Los Angeles CA
International Classification:

H01L 21/338
US Classification:

438182, 438172, 257E21403
Abstract:

A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

Club Extension To A T-Gate High Electron Mobility Transistor
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US Patent:

20090267115, Oct 29, 2009
Filed:

Apr 28, 2008
Appl. No.:

12/150417
Inventors:

Carol Osaka Namba - Walnut CA, US
Po-Hsin Liu - Anaheim CA, US
Ioulia Smorchkova - Lakewood CA, US
Michael Wojtowicz - Long Beach CA, US
Robert Coffie - Camarillo CA, US
Yaochung Chen - Rancho Palos Verdes CA, US
International Classification:

H01L 29/778
H01L 21/338
US Classification:

257194, 438172, 257E21173, 257E29246
Abstract:

A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.

Method Of Forming A Gate Contact
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US Patent:

20140264448, Sep 18, 2014
Filed:

Mar 15, 2013
Appl. No.:

13/837856
Inventors:

CAROL O. NAMBA - Walnut CA, US
Po-Hsin Lin - Anahiem CA, US
Poust Sumiko - Hawthorne CA, US
Ioulia Smorchkova - Lakewood CA, US
Michael Wojtowicz - Long Beach CA, US
Ronald Grundbacher - Oberrieden, CH
Assignee:

Northrop Grumman Systems Corporation - Falls Church VA
International Classification:

H01L 29/778
H01L 29/66
US Classification:

257194, 438172
Abstract:

A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.