Cathy Yen Ly

US Patent:

6894473, May 17, 2005

Filed:

Mar 5, 2003

Appl. No.:

10/379744

Inventors:

Binh Quang Le - San Jose CA, US
Cathy Thuvan Ly - Santa Clara CA, US
Lee Cleveland - Santa Clara CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G05F003/16

US Classification:

323314, 323315, 327539, 327541, 327542

Abstract:

A bandgap reference circuit includes a current generation circuit connected to a voltage generation circuit connected to a smart clamping circuit, and a discharge circuit connected to the current generation circuit and the voltage generation circuit. The discharge circuit initially discharges a potential in the current and voltage generation circuits to improve repeatability. A start circuit within the current generation circuit then initializes the reference output at about the supply voltage to improve the speed and settling time of the output signal. The current generation circuit sources a current to the voltage generation circuit that translates the current having a positive function of temperature +Tinto a reference voltage. The smart clamping circuit further generates a clamping voltage having a negative function of temperature −Tand a load resistance. The clamping voltage and the load resistance are applied across the reference voltage quickly reducing the reference voltage particularly at high temperatures and during start-up to a final level, thereby producing a fast and stable reference voltage.

US Patent:

20040196093, Oct 7, 2004

Filed:

Apr 3, 2003

Appl. No.:

10/406415

Inventors:

Binh Le - San Jose CA, US
Cathy Ly - Santa Clara CA, US
Lee Cleveland - Santa Clara CA, US

International Classification:

H03K003/01

US Classification:

327/536000

Abstract:

Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing. The voltage boost circuit is operable to receive the one or more output signals from the supply voltage detection circuit and alter a boost gain of the multi-stage voltage boost circuit based on the one or more output signals, thereby causing the boosted word line voltage to be substantially independent of the supply voltage value.