Cecil A Branson

US Patent:

56596782, Aug 19, 1997

Filed:

Jan 6, 1995

Appl. No.:

8/369624

Inventors:

Frederick John Aichelmann - Hopewell Junction NY
Cecil Alva Branson - Manassas VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100
G06F 1130

US Classification:

39518301

Abstract:

A fault tolerant memory system is described including a plurality of memory chips arranged to produce an array of addressable locations. Each addressable location comprises a plurality of data bits and a plurality of check bits for checking the integrity of all the data bits and check bits at a given addressable location. A pool of spare chips including at least two spare chips are available for assignment to replace any of said memory chips or a previously assigned spare chip in the event that a chip failure is identified. Means for detecting and assigning spares, in response to the data bits and the check bits read from a given location in memory, is provided for detecting a failing memory chip or previously assigned spare chip and for assigning a previously unassigned spare chip to replace the failing memory chip or previously assigned spare chip.

US Patent:

54348684, Jul 18, 1995

Filed:

Aug 30, 1993

Appl. No.:

8/113005

Inventors:

Frederick J. Aichelmann - Hopewell Junction NY
Cecil A. Branson - Manassas VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1120

US Classification:

371 101

Abstract:

A fault tolerant memory system including a plurality of memory chips arranged to produce an array of addressable locations. Each addressable location has a plurality of data bits and a plurality of check bits for checking the integrity of all the data bits and check bits at a given addressable location. A pool of spare chips including at least two spare chips are available for assignment to replace any of the memory chips or a previously assigned spare chip in the event that a chip failure is identified. A memory maintenance facility for detecting and assigning spares, in response to the data bits and the check bits read from a given location in memory, is provided for detecting a failing memory chip or previously assigned spare chip and for assigning a previously unassigned spare chip to replace the failing memory chip or previously assigned spare chip.