Chad Jonathan Larson

US Patent:

6757617, Jun 29, 2004

Filed:

Jan 23, 2001

Appl. No.:

09/768074

Inventors:

Robert Christopher Dixon - Austin TX
Chad J. Larson - Ames IA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G05D 2300

US Classification:

702 25, 702 34, 702 41, 702 64, 702 65, 702 66, 702 69, 702 70

Abstract:

A multiple fan monitoring circuit for use with a plurality of fans, wherein each of the fans operates at a different frequency and generates a tach signal indicative of the fan operation, including a number of waveform shaping networks coupled to a corresponding one of the fans and utilized to waveshape a tach signal generated by its corresponding fan. The multiple fan monitoring circuit also includes a frequency processing circuit, coupled to the waveform shaping networks, that receives the waveshaped tach signals at a single sense node. The frequency processing circuit includes a summing circuit, coupled to the single sense node, that combines the waveshaped tach signals into a single combined signal, and a frequency discriminator, coupled to the summing circuit, that separates the single combined signal into multiple components, wherein each of the multiple components corresponds to a particular fan.

US Patent:

7653773, Jan 26, 2010

Filed:

Oct 3, 2007

Appl. No.:

11/866472

Inventors:

Chad J. Larson - Austin TX, US
Ricardo Mata, Jr. - Pflugerville TX, US
Michael A. Perez - Cedar Park TX, US
Steven Vongvibool - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

710313, 710 29, 714 43

Abstract:

In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.

US Patent:

7660925, Feb 9, 2010

Filed:

Apr 17, 2007

Appl. No.:

11/736024

Inventors:

Chad J. Larson - Austin TX, US
Ricardo Mata, Jr. - Pflugerville TX, US
Michael A. Perez - Cedar Park TX, US
Steven Vongvibool - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00
G06F 13/38

US Classification:

710107, 710104, 710300

Abstract:

Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

US Patent:

7757017, Jul 13, 2010

Filed:

May 15, 2007

Appl. No.:

11/748781

Inventors:

Chad J. Larson - Austin TX, US
Ricardo Mata, Jr. - Pflugerville TX, US
Michael A. Perez - Cedar Park TX, US
Steven Vongvibool - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00
G06F 5/00
G06F 11/00
G01R 31/08
G08C 15/00
H04J 1/16
H04J 3/14
H04L 1/00
H04L 12/26

US Classification:

710 29, 710 38, 370237

Abstract:

Mechanisms for adjusting direction of data flow between input/output (I/O) bridges and I/O hubs based on real time traffic levels are provided. The mechanisms of the illustrative embodiments provide firmware and/or hardware for monitoring data flow through an I/O bridge loop and corresponding I/O hub in order to determine if a condition exists requiring reassignment of the direction each I/O bridge sends its data. In particular, the firmware/hardware determines whether a current traffic condition through the I/O bridges and I/O hub meets criteria indicative of one pathway through the I/O bridge loop being over-utilized while another pathway through the I/O bridge loop is under-utilized. If it is determined that such a condition exists, the configuration of the I/O bridges may be automatically modified to reassign which pathway is utilized by the I/O bridge in sending/receiving I/O data traffic through the I/O bridge loop.

US Patent:

20080301350, Dec 4, 2008

Filed:

May 31, 2007

Appl. No.:

11/755882

Inventors:

Chad J. Larson - Austin TX, US
Ricardo Mata - Pflugerville TX, US
Michael A. Perez - Cedar Park TX, US
Steven Vongvibool - Austin TX, US

International Classification:

G06F 13/20

US Classification:

710313

Abstract:

A system for reassigning root complex resources in a multi-root PCI express system identifies resources from a lower performing root complex port and reassigns those resources to the higher performing root complex. The system does not change the number of PCI Express lanes, the resources each root complex uses may be reassigned to allow those resources to be translated to available credits for an endpoint. For example, in one embodiment, two root complexes are configured as x8 root complexes with the root complex resources distributed across the two root complexes based upon the usage of the root complex resources.