Chad B Mcbride

US Patent:

6453366, Sep 17, 2002

Filed:

Feb 18, 1999

Appl. No.:

09/251043

Inventors:

Robert Neal Carlton Broberg, III - Rochester MN
Jonathan William Byrn - Kasson MN
Chad B. McBride - Rochester MN
Gary Paul McClannahan - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1328

US Classification:

710 26, 710 28

Abstract:

A method and apparatus are provided for implementing direct memory access (DMA) with dataflow blocking for users for processing data communications in a communications system. A DMA starting address register receives an initial DMA starting address and a DMA length register receives an initial DMA length. A DMA state machine receives a control input for starting the DMA. The DMA state machine updates the DMA starting address to provide a current DMA starting address. The DMA state machine loads a DMA ending address. A DMA blocking logic receives the current DMA starting address and the DMA ending address and blocks received memory requests only within a current active DMA region.

US Patent:

6601122, Jul 29, 2003

Filed:

Apr 17, 2000

Appl. No.:

09/550753

Inventors:

Jonathan W. Byrn - Kasson MN
Chad B. McBride - Rochester MN
Gary P. McClannahan - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1324

US Classification:

710266, 710269, 710 50

Abstract:

A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a power-on default address associated with the same interrupt service routine. The method may determine whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Override address registers are accessed via the special purpose registers of the processing unit. A validation bit may be turned on in response to the setting of the override address, with both the default address and the override address being provided as separate inputs to a multiplexing device controlled by the validation bit. The override address is forwarded from the multiplexing device to an instruction fetch unit whenever the validation bit has been set. The result is decreased latency associated with interrupt handling, and increased flexibility in user definition of critical versus non-critical interrupts.

US Patent:

6836767, Dec 28, 2004

Filed:

Oct 3, 2001

Appl. No.:

09/970002

Inventors:

Chad B. McBride - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1518

US Classification:

706 41

Abstract:

In a first aspect, a pipelined hardware implementation of a neural network circuit includes an input stage, two or more processing stages and an output stage. Each processing stage includes one or more processing units. Each processing unit includes storage for weighted values, a plurality of multipliers for multiplying input values by weighted values, an adder for adding products outputted from product multipliers, a function circuit for applying a non-linear function to the sum outputted by the adder, and a register for storing the output of the function circuit.

US Patent:

7149218, Dec 12, 2006

Filed:

Dec 5, 2001

Appl. No.:

10/006604

Inventors:

Chad B. McBride - Rochester MN, US
Jonathan W. Byrn - Kasson MN, US
Gary P. McClannahan - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/28

US Classification:

370392, 711114, 370428

Abstract:

A method and apparatus for a cache line cut through reduces the latency and memory bandwidth of a data processing system. By cutting through or forwarding a cache line to the next processing element, data that has been read from a local memory into a local cache and altered by a processing element need not be restored to the local memory before it is sent to its destination target processing element. By eliminating the write back to the local memory for direct write through to the destination, performance is increased because the bandwidth and latency are decreased. In a preferred embodiment, the processing elements may be contained within a network processor and the altered data may be a header in one network protocol which needs to be modified to another protocol before transfer of the data along the network. Transfer of the data may be to another network processor, another processing element, or to another memory.

US Patent:

7330479, Feb 12, 2008

Filed:

Sep 25, 2003

Appl. No.:

10/670711

Inventors:

Kenneth J. Barker - Holly Springs NC, US
Chad B. McBride - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/56
H04L 12/28

US Classification:

370419, 370235

Abstract:

In a first aspect, a first method is provided for controlling the flow of data between a first and second clock domain. The first method includes the steps of (1) selecting one of a plurality of ports included in a physical layer interface in the second clock domain to which to send data; and (2) transmitting data from a transmit buffer in the first clock domain to the selected port in the physical layer interface in the second clock domain. Numerous other aspects are provided.

US Patent:

7398505, Jul 8, 2008

Filed:

Feb 7, 2006

Appl. No.:

11/348877

Inventors:

Mark S. Fredrickson - Rochester MN, US
Glen Howard Handlogten - Rochester MN, US
Chad B. McBride - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 18, 716 2

Abstract:

An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.

US Patent:

7430699, Sep 30, 2008

Filed:

Feb 7, 2006

Appl. No.:

11/348907

Inventors:

Mark S. Fredrickson - Rochester MN, US
Chad B. McBride - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714731, 714729, 716 10

Abstract:

An apparatus, program product and method utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches to individual scan chains to optimize the layout of the scan chains in a scan architecture for an integrated circuit design.

US Patent:

7472227, Dec 30, 2008

Filed:

Aug 11, 2005

Appl. No.:

11/201971

Inventors:

Chad B. McBride - Rochester MN, US
Andrew H. Wottreng - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711133, 711135, 711156, 711206, 711207

Abstract:

In a first aspect, a first method is provided for removing entries from an address cache. The first method includes the steps of (1) writing data to a register; and (2) removing a plurality of address cache entries from the address cache based on the data written to the register. Numerous other aspects are provided.