Chai E Gill

US Patent:

7723823, May 25, 2010

Filed:

Jul 24, 2008

Appl. No.:

12/178800

Inventors:

Chai Ean Gill - Chandler AZ, US
Changsoo Hong - Phoenix AZ, US
James D. Whitfield - Gilbert AZ, US
Rouying Zhan - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/62

US Classification:

257565, 257557, 257592, 257593, 257362, 257355, 257E27023, 257E29174, 257E27053, 257577, 257360

Abstract:

An improved lateral bipolar electrostatic discharge (ESD) protection device () comprises a semiconductor (SC) substrate (), an overlying epitaxial SC layer (), emitter-collector regions () laterally spaced apart by a first distance () in the SC layer, a base region () adjacent the emitter region () extending laterally toward and separated from the collector region () by a base-collector spacing () that is selected to set the desired trigger voltage Vt. By providing a buried layer region () under the emitter region () Ohmically coupled thereto, but not providing a comparable buried layer region () under the collector region (), an asymmetrical structure is obtained in which the DC trigger voltage (Vt) and transient trigger voltage (Vt) are closely matched so that |Vt−Vt|0. This close matching increases the design margin and provides a higher performance ESD device () that is less sensitive to process variations, thereby improving manufacturing yield and reducing cost.

US Patent:

8193560, Jun 5, 2012

Filed:

Jun 18, 2009

Appl. No.:

12/487031

Inventors:

Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US
Rouying Zhan - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/66

US Classification:

257173, 257355, 257356, 257357

Abstract:

An electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, comprises, first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first width and second width. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vtl and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vtl, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

US Patent:

8242566, Aug 14, 2012

Filed:

Jan 19, 2010

Appl. No.:

12/689666

Inventors:

Rouying Zhan - Gilbert AZ, US
Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US

Assignee:

Freescale Semiconductors, Inc. - Austin TX

International Classification:

H01L 21/8222

US Classification:

257355, 257106, 257E21608, 361 56

Abstract:

A stacked electrostatic discharge (ESD) protection clamp (-) for protecting associated devices or circuits () comprises two or more series coupled (stacked) bipolar transistors () whose individual trigger voltages Vt depend on their base-collector spacing D. A first (--) of the transistors () has a spacing Dchosen within a D range Z whose slope (ΔVt/ΔD) has a first value (ΔVt/ΔD), and a second (--) of the transistors () has a spacing value Dchosen within a D range Z or Z whose slope (ΔVt/ΔD) has a second value (ΔVt/ΔD)less than the first value (ΔVt/ΔD). The sensitivity of the ESD stack trigger voltage Vtto base-collector spacing variations ΔD during manufacture is much reduced, for example, by as much as 50% for a 2-stack and more for 3-stacks and beyond. A wide range of Vtvalues can be obtained that are less sensitive to unavoidable manufacturing spacing variations ΔD.

US Patent:

8279566, Oct 2, 2012

Filed:

Apr 30, 2008

Appl. No.:

12/112209

Inventors:

James D. Whitfield - Gilbert AZ, US
Chai Ean Gill - Chandler AZ, US
Abhijat Goyal - Chandler AZ, US
Rouying Zhan - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H02H 9/00

US Classification:

361 56

Abstract:

An electrostatic discharge (ESD) clamp (), coupled across input-output (I/O) () and common (GND) () terminals of a protected semiconductor SC device or IC (), comprises, an ESD transistor (ESDT) () with source-drain () coupled between the GND () and I/O (), a first resistor () coupled between gate () and source () and a second resistor () coupled between ESDT body () and source (). Paralleling the resistors () are control transistors () with gates () coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC () is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc. , the ESD trigger voltage Vt is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT () during normal operation is much reduced.

US Patent:

8390071, Mar 5, 2013

Filed:

Nov 30, 2010

Appl. No.:

12/956686

Inventors:

Rouying Zhan - Gilbert AZ, US
Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/62
H01L 21/8222

US Classification:

257361, 438331

Abstract:

A stackable electrostatic discharge (ESD) protection clamp () for protecting a circuit core () comprises, a bipolar transistor () having a base region () with a base contact () therein and an emitter () spaced a lateral distance Lbe from the base contact (), and a collector () proximate the base region (). The base region () comprises a first portion () including the base contact () and emitter (), and a second portion () with a lateral boundary () separated from the collector () by a breakdown region () whose width D controls the clamp trigger voltage, the second portion () lying between the first portion () and the boundary (). The damage-onset threshold current It of the ESD clamp () is improved by increasing the parasitic resistance Rbe of the emitter-base region (), by for example, increasing Lbe or decreasing the relative doping density of the first portion () or a combination thereof.

US Patent:

8390092, Mar 5, 2013

Filed:

Nov 12, 2010

Appl. No.:

12/944931

Inventors:

Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US
Vadim A. Kushner - Tempe AZ, US
Rouying Zhan - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/58

US Classification:

257487, 257111, 257577, 257E21042, 257E21051, 257E21058, 257E21126, 257E21127, 257E21135, 257E21608, 438289, 438328

Abstract:

An area-efficient, high voltage, single polarity ESD protection device () is provided which includes an p-type substrate (); a first p-well (-) formed in the substrate and sized to contain n+ and p+ contact regions () that are connected to a cathode terminal; a second, separate p-well (-) formed in the substrate and sized to contain only a p+ contact region () that is connected to an anode terminal; and an electrically floating n-type isolation structure (-) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

US Patent:

8432654, Apr 30, 2013

Filed:

Sep 12, 2012

Appl. No.:

13/612466

Inventors:

James D. Whitfield - Gilbert AZ, US
Chai Ean Gill - Chandler AZ, US
Abhijat Goyal - Chandler AZ, US
Rouying Zhan - Gilbert AZ, US

Assignee:

Freescale Semiconductor Inc. - Austin TX

International Classification:

H02H 9/00

US Classification:

361 56, 361 911, 361111

Abstract:

An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc. , the ESD trigger voltage Vt is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

US Patent:

8455306, Jun 4, 2013

Filed:

May 25, 2012

Appl. No.:

13/480924

Inventors:

Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US
Rouying Zhan - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/332
H01L 21/00
H01L 27/02

US Classification:

438133, 438400, 438 10, 257587, 257592, 257173, 257355, 257577, 257546, 257357

Abstract:

Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.