Chan Young Lee

US Patent:

6338132, Jan 8, 2002

Filed:

Dec 30, 1998

Appl. No.:

09/223299

Inventors:

Alan B. Kyker - Portland OR
Per Hammarlund - Hillsboro OR
Chan Lee - Portland OR
Robert F. Krick - Fort Collins CO
Hitesh Ahuja - Portland OR
William Alexander - Hillsboro OR
Joseph Rohlman - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 900

US Classification:

712211, 712213

Abstract:

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

US Patent:

6442674, Aug 27, 2002

Filed:

Dec 30, 1998

Appl. No.:

09/223297

Inventors:

Chan Lee - Portland OR
Hitesh Ahuja - Portland OR
Robert F. Krick - Fort Collins CO

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9315

US Classification:

712205

Abstract:

A method and system for reducing a latency of microprocessor instructions in transit along an instruction pipeline of a microprocessor by bypassing, at certain times, a fill buffer located between an instruction source and a trace cache unit on the instruction pipeline. The signal path through the fill buffer to the trace cache unit represent a first signal path. In the instruction pipeline, a second signal path is also provided, one which also leads instructions to the trace cache unit, not through the fill buffer, but through a latch provided on the second instruction path. If the latch is enabled, a set of instructions appearing at the input of the fill buffer is transmitted through the latch along the second instruction path and to the trace cache. As a result, the fill buffer is bypassed and a reduced latency for the bypassed instructions is achieved along the instruction pipeline.

US Patent:

6457119, Sep 24, 2002

Filed:

Jul 23, 1999

Appl. No.:

09/360192

Inventors:

Darrell Boggs - Aloha OR
Robert F. Krick - Fort Collins CO
Chan Lee - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 938

US Classification:

712227, 712231

Abstract:

Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled. Briefly, in accordance with one more embodiment of the invention, a system includes: a processor with a microcode source capable of detecting the occurrence of at least one corrupted microcode instruction and signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. The system employing the processor further includes main memory, a video card, a system bus, and bulk storage capability.

US Patent:

6493797, Dec 10, 2002

Filed:

Mar 31, 2000

Appl. No.:

09/540431

Inventors:

Chan Lee - Portland OR
Richard A. Weier - Bolton MA
Robert F. Krick - Fort Collins CO

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711118, 711136, 711144, 711145

Abstract:

A method and device are provided for reading data from a trace cache in a manner that reduces the time and power consumed by such an operation. A mini-tag is provided for comparing to a requested address to reduce the amount of data that must be read. Mini-tag read and compare operations may be performed in parallel to a full tag read operation, and a data read operation of only the data identified by a matching mini-tag may be performed in parallel to a full tag compare operation. A victim selection method for writing data into the trace cache is used to maintain the uniqueness of the mini-tags.

US Patent:

6594734, Jul 15, 2003

Filed:

Dec 20, 1999

Appl. No.:

09/466687

Inventors:

Alan Kyker - Portland OR
Chan Lee - Portland OR
Vihang D. Pandya - Beaverton OR
Roshan Fernando - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711146, 711207, 711144, 711125

Abstract:

Self modifying code is detected using a translation lookaside buffer in order to provide cache coherency. The translation lookaside buffer has physical page addresses stored therein over which snoops can be performed using the physical memory address of a store into memory. The translation lookaside buffer includes a content addressable memory which not only provides page translation but provides content addressability based on the physical page addresses stored therein. If a match occurs during a snoop using the translation lookaside buffer, it is possible that an SMC occurred within the page of locations stored in memory associated with the matched physical page addresses. To provide finer granularity than a page of addresses, FINE HIT bits are included with each entry in the cache associating information in the cache to portions of a page within memory. Snoop logic performs the comparison of the FINE HIT bits with the respective lower order bits of the physical address to determine if a self modifying code condition has occurred within the portion of memory that may be stored in the cache.

US Patent:

6711669, Mar 23, 2004

Filed:

Jan 10, 2003

Appl. No.:

10/339571

Inventors:

Alan B. Kyker - Portland OR
Per Hammarlund - Hillsboro OR
Chan Lee - Portland OR
Robert F. Krick - Fort Collins CO
Hitesh Ahuja - Portland OR
William Alexander - Hillsboro OR
Joseph Rohlman - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 900

US Classification:

712211, 712213

Abstract:

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

US Patent:

7114057, Sep 26, 2006

Filed:

Oct 30, 2001

Appl. No.:

09/984525

Inventors:

Alan B. Kyker - Portland OR, US
Per Hammarlund - Hillsboro OR, US
Chan Lee - Portland OR, US
Robert F. Krick - Fort Collins CO, US
Hitesh Ahuja - Portland OR, US
William Alexander - Hillsboro OR, US
Joseph Rohlman - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/318
G06F 9/28

US Classification:

712213, 712211

Abstract:

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

US Patent:

7321963, Jan 22, 2008

Filed:

Feb 5, 2004

Appl. No.:

10/773848

Inventors:

Alan B. Kyker - Portland OR, US
Per Hammarlund - Hillsboro OR, US
Chan Lee - Portland OR, US
Robert F. Krick - Fort Collins CO, US
Hitesh Ahuja - Portland OR, US
William Alexander - Hillsboro OR, US
Joseph Rohlman - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/318
G06F 9/28

US Classification:

712213, 712211

Abstract:

An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.