Chanh Nguyen

US Patent:

6482711, Nov 19, 2002

Filed:

Oct 28, 1999

Appl. No.:

09/428820

Inventors:

Chanh Nguyen - Calabasas CA
Daniel P. Docter - Santa Monica CA

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 21331

US Classification:

438317, 438312

Abstract:

Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and p-type InAs is used to create extremely high speed bipolar devices which, due to reduced turn-on voltages, lend themselves to circuits having drastically reduced power dissipation. The described HBTs are fabricated on InAs or GaSb substrates, and include an InPSb emitter. The base includes In and As, in the form of InAs when on an InAs substrate, and as InAsSb when on a GaSb substrate. The collector may be the same as the base to form a single heterojunction bipolar transistor (SHBT) or may be the same as the emitter to form a double heterojunction bipolar transistor (DHBT). Heterojunctions preferably include a grading layer, which may be implemented by continuously changing the bulk material composition, or by forming a chirped superlattice of alternating materials. The grading layer preferably has delta doping planes near its ends to form an electrostatic gradient offsetting the quasi-electric field variation due to the changes in material composition, whereby effective conduction band offset may be substantially eliminated to facilitate speed, and valence band offset increased proportionally to enhance gain.

US Patent:

6635907, Oct 21, 2003

Filed:

Nov 17, 1999

Appl. No.:

09/441903

Inventors:

Chanh N. Nguyen - Calabasas CA
Joel N. Schulman - Malibu CA
David H. Chow - Newbury Park CA

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 29772

US Classification:

257183, 257185

Abstract:

A backward diode including a heterostructure consisting of a first layer of InAs and second layer of GaSb or InGaSb with an interface layer consisting of an aluminum antimonide compound is presented. It is also disclosed that the presence of AlSb in the interface enhances the highly desirable characteristic of nonlinear current-voltage (I-V) curve near zero bias. The backward diode is useful in radio frequency detection and mixing. The interface layer may be one or more layers in thickness, and may also have a continuously graded AlGaSb layer with a varying Al concentration in order to enhance the nonlinear I-V curve characteristic near zero bias.

US Patent:

6673265, Jan 6, 2004

Filed:

Aug 3, 2000

Appl. No.:

09/632272

Inventors:

Chanh Nguyen - Calabasas CA

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 310328

US Classification:

252183, 257200, 257201, 257 11, 257 12, 257 14, 257191, 257480

Abstract:

The present invention provides a varactor diode for frequency multipliers at submillimeter wave frequencies and above. Functionally the new diode replaces the conventional heterostructure barrier varactor diode. Two important features of the antimony-based quantum well heterostructure barrier varactor are; first: an aluminum antimnide/aluminum-arsenic-antimnide heterostructure barrier and second: a bandgap-engineered, triangular quantum well cathode and anode.

US Patent:

6806512, Oct 19, 2004

Filed:

Oct 3, 2002

Appl. No.:

10/264602

Inventors:

Chanh Nguyen - Calabasas CA
Daniel P. Docter - Santa Monica CA

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 29737

US Classification:

257197, 257198, 257201, 438312, 438317

Abstract:

Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and -type InAs is used to create extremely high speed bipolar devices which, due to reduced turn-on voltages, lend themselves to circuits having drastically reduced power dissipation. The described HBTs are fabricated on InAs or GaSb substrates, and include an InPSb emitter. The base includes In and As, in the form of InAs when on an InAs substrate, and as InAsSb when on a GaSb substrate. The collector may be the same as the base to form a single heterojunction bipolar transistor (SHBT) or may be the same as the emitter to form a double heterojunction bipolar transistor (DHBT). Heterojunctions preferably include a grading layer, which may be implemented by continuously changing the bulk material composition, or by forming a chirped superlattice of alternating materials. The grading layer preferably has delta doping planes near its ends to form an electrostatic gradient offsetting the quasi-electric field variation due to the changes in material composition, whereby effective conduction band offset may be substantially eliminated to facilitate speed, and valence band offset increased proportionally to enhance gain.

US Patent:

6897137, May 24, 2005

Filed:

Jun 19, 2003

Appl. No.:

10/600521

Inventors:

Nguyen Xuan Nguyen - Granada Hills CA, US
Paul Hashimoto - Los Angeles CA, US
Chanh N. Nguyen - Calabasas CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L021/28

US Classification:

438602, 438605, 438610, 438652, 438658, 438666

Abstract:

A process for fabricating ohmic contacts in a field-effect transistor includes the steps of: thinning a semiconductor layer forming recessed portions in the semiconductor layer; depositing ohmic contact over the recessed portions; and heating the deposited ohmic contacts. The field-effect transistor comprises a layered semiconductor structure which includes a first group III nitride compound semiconductor layer doped with a charge carrier, and a second group III nitride compound semiconductor layer positioned below the first layer, to generate an electron gas in the structure. After the heating step the ohmic contacts communicate with the electron gas. As a result, an excellent ohmic contact to the channel of the transistor is obtained.

US Patent:

7700974, Apr 20, 2010

Filed:

Apr 14, 2005

Appl. No.:

11/107485

Inventors:

Nguyen Xuan Nguyen - Granada Hills CA, US
Paul Hashimoto - Los Angeles CA, US
Chanh H. Nguyen - Calabasas CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 29/778

US Classification:

257194, 257E29249

Abstract:

A process for fabricating ohmic contacts in a field-effect transistor includes the steps of: thinning a semiconductor layer forming recessed portions in the semiconductor layer; depositing ohmic contact over the recessed portions; and heating the deposited ohmic contacts. The field-effect transistor comprises a layered semiconductor structure which includes a first group III nitride compound semiconductor layer doped with a charge carrier, and a second group III nitride compound semiconductor layer positioned below the first layer, to generate an electron gas in the structure. After the heating step the ohmic contacts communicate with the electron gas. As a result, an excellent ohmic contact to the channel of the transistor is obtained.

US Patent:

20040021152, Feb 5, 2004

Filed:

Aug 5, 2002

Appl. No.:

10/214422

Inventors:

Chanh Nguyen - Calabasas CA, US
Jeong-Sun Moon - Chatsworth CA, US
Wah Wong - Montebello CA, US
Miro Micovic - Newbury Park CA, US
Paul Hashimoto - Los Angeles CA, US

International Classification:

H01L031/0328

US Classification:

257/192000

Abstract:

The present invention utilizes the strong piezoelectric effect, found in group-III nitride materials to circumvent the need to selectively remove Gallium Nitride (GaN) in the fabrication of GaN/AlGaN Heterostructure Field Effect Transistors. The transistor is comprised of a semi-insulating substrate a buffer layer which is in continual contact with the semi-insulating substrate A GaN active channel is atop the buffer layer An AlGaN barrier in laid on top of, and is in continual contact with, the GaN active channel Thereafter, there is a source contact and a drain contact both in physical contact with the GaN active channel There is a gate upon the AlGaN barrier and between the source contact and a drain contact At least one dielectric stressor is placed upon the AlGaN barrier The dielectric stressors are between the gate and the source and drain contacts.

US Patent:

56635834, Sep 2, 1997

Filed:

Jun 6, 1995

Appl. No.:

8/466157

Inventors:

Mehran Matloubian - Encino CA
Takyiu Liu - Newbury Park CA
Chanh Nguyen - Newbury Park CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H01L 310328
H01L 2120

US Classification:

257192

Abstract:

An epitaxial structure and method of manufacture for a field-effect transistor capable of low-noise and power applications. Preferably, the epitaxial structure includes an N-type barrier layer comprising a wide-gap semiconductor material having the formula Al. sub. 1-y Ga. sub. y P. sub. 71+z Sb. sub. 29-z.