Chao-Yang Lu

from Sunnyvale, CA

Chao-Yang Lu Phones & Addresses

  • Sunnyvale, CA

Work

  • Company:
    Broadcom
    Nov 2010
  • Position:
    Principle engineer

Education

  • Degree:
    phD
  • School / High School:
    Purdue University
    1998 to 2003
  • Specialities:
    electrical engineering

Skills

Semiconductors • Ic • Silicon • Cmos • Design of Experiments • Integration • Semiconductor Industry • Thin Films • Simulations • Failure Analysis • Cross Functional Team Leadership • Mixed Signal • Process Integration • Analog • Asic • Soc

Languages

English

Industries

Semiconductors

Resumes

Chao-Yang Lu Photo 1

Master Engineer, Central Engineering

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Location:
903 Anaconda Way, Sunnyvale, CA 94087
Industry:
Semiconductors
Work:
Broadcom since Nov 2010
Principle engineer

UMC (UMC-USA) Jul 2009 - Nov 2010
Sr. manager

Mosel Vitelic / PROMOS Nov 2007 - May 2009
Device manager

INTEL / CTM integration Oct 2003 - Oct 2007
Sr. device engineer
Education:
Purdue University 1998 - 2003
phD, electrical engineering
National Taiwan University
Skills:
Semiconductors
Ic
Silicon
Cmos
Design of Experiments
Integration
Semiconductor Industry
Thin Films
Simulations
Failure Analysis
Cross Functional Team Leadership
Mixed Signal
Process Integration
Analog
Asic
Soc
Languages:
English

Us Patents

  • Metal Finger Capacitor For High-K Metal Gate Processes

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  • US Patent:
    20130113077, May 9, 2013
  • Filed:
    Dec 28, 2011
  • Appl. No.:
    13/338492
  • Inventors:
    Agnes Neves WOO - Encino CA, US
    Pascal Tran - Irvine CA, US
    Akira Ito - Irvine CA, US
    Chao-Yang Lu - Sunnyvale CA, US
    Jung Wang - Laguna Niguel CA, US
  • Assignee:
    Broadcom Corporation - Irvine CA
  • International Classification:
    H01L 29/02
  • US Classification:
    257532, 257E29002
  • Abstract:
    Embodiments described herein provide a structure for finger capacitors, and more specifically metal-oxide-metal (“MOM”) finger capacitors and arrays of finger capacitors. A plurality of Shallow Trench Isolation (STI) formations is associated with every other column of capacitor fingers, with poly fill formations covering the STI formations to provide a more robust and efficient structure.
  • Field Transistor Structure Manufactured Using Gate Last Process

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  • US Patent:
    20130001574, Jan 3, 2013
  • Filed:
    Jun 30, 2011
  • Appl. No.:
    13/174083
  • Inventors:
    Chao-Yang Lu - Sunnyvale CA, US
    Akira Ito - Irvine CA, US
  • Assignee:
    Broadcom Corporation - Irvine CA
  • International Classification:
    H01L 29/78
    H01L 21/28
  • US Classification:
    257 66, 438586, 257E29255, 257E2119
  • Abstract:
    According to embodiments of the invention, a field transistor structure is provided. The field transistor structure includes a semiconductor substrate, a metal gate, a polycrystalline silicon (polysilicon) layer, and first and second metal portions. The polysilicon layer has first, second, third, and fourth sides and is disposed between the semiconductor substrate on the first side and the metal gate on the second side. The polysilicon layer is also disposed between the first and second metal portions on the third and fourth sides. According to some embodiments of the present invention, the field transistor structure may also include a thin metal layer disposed between the polysilicon layer and the semiconductor substrate. The thin metal layer may be electronically coupled to each of the first and second metal portions.
  • Gate Substantial Contact Based One-Time Programmable Device

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  • US Patent:
    20150194433, Jul 9, 2015
  • Filed:
    Jan 8, 2014
  • Appl. No.:
    14/150245
  • Inventors:
    - IRVINE CA, US
    CHAO-YANG LU - SUNNYVALE CA, US
  • Assignee:
    BROADCOM CORPORATION - IRVINE CA
  • International Classification:
    H01L 27/112
    H01L 21/768
    H01L 29/78
    G11C 17/12
  • Abstract:
    A field-effect transistor (FET) based one-time programmable (OTP) device is discussed. The OTP device includes a fin structure, a gate structure, a first contact region, and a second contact region. The first contact region includes an insulating region and a conductive region and is configured to be electrically isolated from the gate structure. While, the second contact region includes the conductive region and is configured to be electrically coupled to at least a portion of the gate structure. The OTP device is configured to be programmed by disintegration of the insulating region in response to a first voltage being applied to the first contact and a second voltage being applied to the second contact region simultaneously, where the second voltage is higher than the first voltage by a threshold value.

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