Charles Steven Alexander

US Patent:

6430725, Aug 6, 2002

Filed:

Jun 22, 2000

Appl. No.:

09/602203

Inventors:

David A. Reichle - Boise ID
Charles K. Snodgrass - Boise ID
Charles S. Alexander - Boise ID
Fremont S. Smith - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1100

US Classification:

714815, 714700, 714724, 714736, 327261, 713503

Abstract:

Signal alignment circuitry aligns (i e. , deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the mux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock. To control the rising and falling edges of one of the test signals, and thereby align the signal with the other test signals, the control circuitry first sweeps the delay in the rising edge and falling edge delay elements until the latched-in signal transitions.

US Patent:

6754861, Jun 22, 2004

Filed:

Jun 6, 2002

Appl. No.:

10/164975

Inventors:

David A. Reichle - Boise ID
Charles K. Snodgrass - Boise ID
Charles S. Alexander - Boise ID
Fremont S. Smith - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1100

US Classification:

714724, 714700, 714736, 714815, 327261, 713503

Abstract:

Signal alignment circuitry aligns (i. e. , deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the mux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock.

US Patent:

61580309, Dec 5, 2000

Filed:

Aug 21, 1998

Appl. No.:

9/137738

Inventors:

David A. Reichle - Boise ID
Charles K. Snodgrass - Boise ID
Charles S. Alexander - Boise ID
Fremont S. Smith - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 3128

US Classification:

714724

Abstract:

Signal alignment circuitry aligns (i. e. , deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the flux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock. To control the rising and falling edges of one of the test signals, and thereby align the signal with the other test signals, the control circuitry first sweeps the delay in the rising edge and falling edge delay elements until the latched-in signal transitions.

US Patent:

60615095, May 9, 2000

Filed:

Jun 19, 1998

Appl. No.:

9/100440

Inventors:

Charles K. Snodgrass - Boise ID
Robert L. Totorica - Boise ID
David A. Reichle - Boise ID
Charles S. Alexander - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1750

US Classification:

39550013

Abstract:

The present invention provides for a method and an apparatus for routing electrical signals. The method includes accessing a plurality of electrical circuits. The apparatus includes a supervisory circuit capable of delivering two access signals from a group of first, second, third, and fourth access signals, wherein the supervisory circuit is capable of delivering one of the first and third access signals, and one of the second and fourth access signals. A plurality of electrical circuits is organized into first and second rows. A first portion of the plurality of electrical circuits in the first and second rows, is coupled to a first access signal line. A second portion of the plurality of electrical circuits in the first and second rows is coupled to a second access signal line. The first and second portions of the plurality of electrical circuits in said first row are coupled to a third access signal. The first and second portions of said plurality of electrical circuits in the second row are coupled to a fourth access signal.

Address:

2010 S Grassmere St, Boise, ID 83709

VIN:

JTMBK32V575023865

Make:

TOYOTA

Model:

RAV4

Year:

2007