Charles W Archer

US Patent:

7716407, May 11, 2010

Filed:

Jan 3, 2008

Appl. No.:

11/968720

Inventors:

Gheorghe Almasi - Ardsley NY, US
Charles J. Archer - Rochester MN, US
Mark E. Giampapa - Irvington NY, US
Thomas M. Gooding - Rochester MN, US
Philip Heidelberger - Cortlandt Manor NY, US
Jeffrey J. Parker - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/24

US Classification:

710260, 710104

Abstract:

Executing application function calls in response to an interrupt including creating a thread; receiving an interrupt having an interrupt type; determining whether a value of a semaphore represents that interrupts are disabled; if the value of the semaphore represents that interrupts are not disabled: calling, by the thread, one or more preconfigured functions in dependence upon the interrupt type of the interrupt; yielding the thread; and if the value of the semaphore represents that interrupts are disabled: setting the value of the semaphore to represent to a kernel that interrupts are hard-disabled; and hard-disabling interrupts at the kernel.

US Patent:

7827385, Nov 2, 2010

Filed:

Aug 2, 2007

Appl. No.:

11/832918

Inventors:

Gheorghe Almasi - Ardsley NY, US
Charles J. Archer - Rochester MN, US
Joseph D. Ratterman - Rochester MN, US
Brian E. Smith - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/76

US Classification:

712 16, 712 17

Abstract:

A parallel computer comprises a plurality of compute nodes organized into at least one operational group for collective parallel operations. Each compute node is assigned a unique rank and is coupled for data communications through a global combining network. One compute node is assigned to be a logical root. A send buffer and a receive buffer is configured. Each element of a contribution of the logical root in the send buffer is contributed. One or more zeros corresponding to a size of the element are injected. An allreduce operation with a bitwise OR using the element and the injected zeros is performed. And the result for the allreduce operation is determined and stored in each receive buffer.

US Patent:

7984450, Jul 19, 2011

Filed:

Nov 28, 2007

Appl. No.:

11/946136

Inventors:

Gheorghe Almasi - Ardsley NY, US
Charles J. Archer - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

719313, 718106

Abstract:

Methods, apparatus, and products are disclosed for dispatching packets on a global combining network of a parallel computer comprising a plurality of nodes connected for data communications using the network capable of performing collective operations and point to point operations that include: receiving, by an origin system messaging module on an origin node from an origin application messaging module on the origin node, a storage identifier and an operation identifier, the storage identifier specifying storage containing an application message for transmission to a target node, and the operation identifier specifying a message passing operation; packetizing, by the origin system messaging module, the application message into network packets for transmission to the target node, each network packet specifying the operation identifier and an operation type for the message passing operation specified by the operation identifier; and transmitting, by the origin system messaging module, the network packets to the target node.

US Patent:

20090113308, Apr 30, 2009

Filed:

Oct 26, 2007

Appl. No.:

11/924934

Inventors:

Gheorghe Almasi - Ardsley NY, US
Charles J. Archer - Rochester MN, US
Charles C. Erway - Providence RI, US
Brian E. Smith - Rochester MN, US

International Classification:

G06F 17/00
G06F 3/048

US Classification:

715734, 715273

Abstract:

Methods, apparatus, and products are disclosed for creating and administering communications schedules for data communications among compute nodes in a data communications network of a parallel computer that include: receiving a communications schedule specifying data communications steps in a message passing operation performed by the compute nodes in the data communications network of the parallel computer; parsing the communications schedule to identify the data communications steps; and generating a graphical representation of the communications schedule, including graphing the data communications steps for the message passing operation.