Charles F Cassidy

US Patent:

53434269, Aug 30, 1994

Filed:

Jun 11, 1992

Appl. No.:

7/897164

Inventors:

Charles Cassidy - Northboro MA
Paul Kemp - Northboro MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H03M 1300

US Classification:

36518902

Abstract:

A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits--gate arrays--it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly "perfect. " A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data. The added cost of multiple-bit EDC, including the added cost of extra storage for the check bits and the EDC circuit itself, is more than compensated by reduced cost of the DRAMs.

US Patent:

54597420, Oct 17, 1995

Filed:

Mar 14, 1994

Appl. No.:

8/212334

Inventors:

Charles Cassidy - Northboro MA
Paul Kemp - Northboro MA
Donald Smelser - Bolton MA

Assignee:

Quantum Corporation - Milpitas CA

International Classification:

H03M 1300
G06F 1100

US Classification:

371 401

Abstract:

A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits--gate arrays--it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly "perfect. " A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data. The added cost of multiple-bit EDC, including the added cost of extra storage for the check bits and the EDC circuit itself, is more than compensated by reduced cost of the DRAMs.