Charles N Dennis

US Patent:

7969216, Jun 28, 2011

Filed:

Nov 6, 2009

Appl. No.:

12/614247

Inventors:

Charles A. Dennis - Warrenton VA, US
Dale A. Rickard - Manassass VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

H03K 7/00

US Classification:

327161, 327261

Abstract:

Embodiments of a method and system for both open-loop and closed-loop timing synchronization are provided in which a master clock signal, and a plurality of signals that define greater periods of time, are distributed to a plurality of host devices. A frame-sync signal is used to define a “frame” consisting of a predetermined number of clock periods, and a reset signal is used to define a larger period consisting of a predetermined number of frames. Due to a variety of system parameters, the innate delay time associated with each respective timing distribution path may differ. The system is operable to adjust the timing signals propagated to the plurality of host devices along each respective timing distribution path to compensate for these differences so that each host device remains synchronized with all other host devices.

US Patent:

40414612, Aug 9, 1977

Filed:

Jul 25, 1975

Appl. No.:

5/599306

Inventors:

Gary L. Kratz - Warrenton VA
William W. Sproul - Reston VA
Eugene T. Walendziewicz - Wakefield MA
Donald E. Wallis - Marblehead MA
Charles A. Dennis - Warrenton VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 910
G06F 1300

US Classification:

364200

Abstract:

A signal analyzer system is disclosed which includes an arithmetic processor containing a plurality of pipeline processor elements in parallel array with each element connected to a respective working store, with all of the elements being under microprogram control of an arithmetic element controller. A storage controller included in the system is connected to the arithmetic processor, to a system input and to a system ouput. A bulk storage included in the system is connected to the storage controller. The storage controller controls data transfers into and out of the system and between the bulk storage and arithmetic processor. A control processor included in the system is connected to the arithmetic processor and the storage controller by means of a data bus for centrally controlling the operation of the plurality of pipeline processor elements by transmitting micro control words over the bus.