Charles M Flaig

US Patent:

6867780, Mar 15, 2005

Filed:

Dec 6, 1999

Appl. No.:

09/454518

Inventors:

David B. Kirk - San Francisco CA, US
Paolo E. Sabella - Pleasanton CA, US
Charles M. Flaig - San Jose CA, US
Mark J. Kilgard - Cupertino CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F015/80

US Classification:

345505, 345506

Abstract:

A system, method, and article of manufacture are provided for allowing direct memory access to graphics vertex data by a graphics accelerator module. First, vertex data is stored in memory. Next, an index is received which is representative of a portion of the vertex data in the memory. A location is then determined in the memory in which the portion of the vertex data is stored. Such portion of the vertex data may thereafter be directly retrieved from the determined location in the memory while bypassing a processor.

US Patent:

56740778, Oct 7, 1997

Filed:

Sep 30, 1994

Appl. No.:

8/315885

Inventors:

Charles M. Flaig - Cupertino CA
William Todd Krein - San Jose CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

H05K 102

US Classification:

439 63

Abstract:

Connectors on a microcomputer printed circuit board backplane receive slotted insertion of a plurality of device cards containing application specific integrated circuits (ASICs). Interconnection of the device card connectors is accomplished on the surface of the circuit board or internally with an electric line which interleaves the device card connectors providing increased conductor length between physically adjacent connectors, establishing an increased impedance level. The increased physical lengths of the intervening electric lines between the connectors provide increased impedance as seen by inserted device cards, which enhances the matching capabilities of the connectors.

US Patent:

54106770, Apr 25, 1995

Filed:

Dec 30, 1991

Appl. No.:

7/815828

Inventors:

Steven G. Roskowski - Sunnyvale CA
Charles M. Flaig - Cupertino CA
Dean M. Drako - Cupertino CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06F 706

US Classification:

395500

Abstract:

A circuit for translating data in one of a plurality of data formats into data in any of the other of the plurality of the data formats including apparatus for storing data from a first number of input bytes of data, apparatus for selecting unused bytes from the first number of data bytes stored by the apparatus for storing data and from a second number of input bytes of data, apparatus for placing the unused bytes selected in numerical byte order, and apparatus for placing the data in the numerical byte order in byte position for transfer to the format of a destination device.

US Patent:

55577555, Sep 17, 1996

Filed:

Feb 24, 1994

Appl. No.:

8/201461

Inventors:

William T. Krein - San Jose CA
Charles M. Flaig - Cupertino CA
James D. Kelly - Aptos CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06F 1336
G06F 1342

US Classification:

395293

Abstract:

In a bus system including a bus, a plurality of nodes including a primary node, and a bus access coordinator, bus utilization efficiency is improved by operating the coordinator at the same clock frequency as the primary node. The primary node is the node in the bus system which accesses the bus most frequently. By running the coordinator synchronous with the primary node, the need for synchronization events between the two components is eliminated. Since the primary node accesses the bus most frequently, eliminating synchronization events with the primary node eliminates most of the synchronization events in the bus system. Thus, synchronization events are minimized which, in turn, improves bus utilization efficiency.

US Patent:

56921373, Nov 25, 1997

Filed:

May 8, 1995

Appl. No.:

8/436987

Inventors:

Michael L. Regal - Campbell CA
Charles M. Flaig - Cupertino CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06F 1300
G06F 1338
G06F 1340

US Classification:

395309

Abstract:

An interface between two buses in different clock domains. The interface includes a master buffer which is used for both master writes and slave reads. A control logic unit for each bus receives signals from a buffer manager which straddles the clock domains to gate latch pulses to the master buffer.

US Patent:

54737621, Dec 5, 1995

Filed:

Jan 25, 1994

Appl. No.:

8/186381

Inventors:

William T. Krein - San Jose CA
Charles M. Flaig - Cupertino CA
James D. Kelly - Aptos CA

Assignee:

Apple Computer Inc. - Cupertino CA

International Classification:

G06F 1300

US Classification:

395287

Abstract:

A system for pipelining bus requests includes a bus, at least one node coupled to the bus, and a bus coordinator coupled to the node. The node uses a single bus request signal to both request control of the bus from the bus coordinator, and to retain control of the bus. In response to an asserted bus request signal from the node, the coordinator sends an asserted bus grant signal to the node to grant the node control of the bus. This bus grant signal tracks the bus request signal so that as long as the bus request signal remains asserted, the bus grant signal also is asserted. To allow for pipelining, the bus coordinator maintains the bus grant signal in an asserted state for at least one clock cycle after the bus request is deasserted. By holding the bus grant signal in the asserted state for one extra cycle, the coordinator gives the node time to deassert and then to reassert the bus request signal before the bus grant signal changes state. If the bus request is reasserted within the extra cycle, the coordinator continues to maintain the bus grant signal in the asserted state so that no state change is experienced by the bus grant signal between the deassertion and the reassertion of the bus request signal.

US Patent:

58020551, Sep 1, 1998

Filed:

Apr 22, 1996

Appl. No.:

8/635646

Inventors:

William Todd Krein - San Jose CA
Charles M. Flaig - Cupertino CA
James D. Kelly - Aptos CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06F 1300

US Classification:

370402

Abstract:

A bus bridge circuit employs a dynamic allocation scheme that allows read transactions to be pipelined without deadlock and without the need for permanently reserving multiple buffer slots for read response transactions. The bus bridge circuit associates input and output buffers with a node and includes a state machine to monitor the number and type of transaction packets currently in slots that make up the buffers. In particular, the state machine monitors the number of transaction packets loaded in the output buffer slots, the number of outstanding read transactions for the node, and the number of read response transactions currently loaded in the output buffer. The state machine then allows the node to load a READ or WRITE transaction only if the monitored data indicates at least one of the buffer slots will be available to service a READ RESPONSE subsequently loaded by the node. The state machine launches READs to the node only when an unallocated buffer slot is available to service the corresponding READ RESPONSE.

US Patent:

57489173, May 5, 1998

Filed:

Dec 28, 1995

Appl. No.:

8/579884

Inventors:

William Todd Krein - San Jose CA
Charles M. Flaig - Cupertino CA
James D. Kelly - Aptos CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06F 1338

US Classification:

395306

Abstract:

A data system architecture and interface circuits permit slow devices having limited signal capacities to launch and receive information from a central bus. Data is clocked onto the bus with a master circuit at the leading and trailing edges of the bus clock so that portions of a large multibit signal are launched without having to wait for the initiation of a next clock cycle. Accordingly, data portions are launched during both leading and trailing edges of the clock signal. In the case of a simple bus device not able to accommodate inclusion of a slave interface circuit, the received signal packet is provided in adapted form anticipating that only a second half portion of the signal packet will actually be registered as received.