Charles Long Lin

US Patent:

6420225, Jul 16, 2002

Filed:

Mar 13, 2001

Appl. No.:

09/805815

Inventors:

Paul Chang - Saratoga CA
Vladimir Rodov - Redondo Beach CA
Geeng-Chuan Chern - Cupertino CA
Charles Lin - Fremont CA

Assignee:

APD Semiconductor, Inc. - San Jose CA

International Classification:

H01L 218234

US Classification:

438237, 438167, 438173, 438586

Abstract:

A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.

US Patent:

6624030, Sep 23, 2003

Filed:

Dec 19, 2000

Appl. No.:

09/742262

Inventors:

Paul Chang - Saratoga CA
Geeng-Chuan Chern - Cupertino CA
Wayne Y. W. Hsueh - San Jose CA
Vladimir Rodov - Redondo Beach CA
Charles Lin - Fremont CA

Assignee:

Advanced Power Devices, Inc. - San Jose CA

International Classification:

H01L 21336

US Classification:

438268, 438531

Abstract:

A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction separating the channel region from the substrate of first conductivity type. In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

US Patent:

6653227, Nov 25, 2003

Filed:

Aug 31, 2000

Appl. No.:

09/651963

Inventors:

Chung Woh Lai - Singapore, SG
Beichao Zhang - Singapore, SG
Eng Hua Lim - Singapore, SG
Arthur Ang - Singapore, SG
Hai Jiang Peng - Singapore, SG
Charles Lin - Fremont CA

Assignee:

Chartered Semiconductor Manufacturing Ltd. - Singapore

International Classification:

H01L 214763

US Classification:

438633, 438706, 438712, 438719

Abstract:

A new method for forming a high quality cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A thermal oxide layer is grown overlying the semiconductor substrate. A titanium layer is deposited overlying the thermal oxide layer. A cobalt layer is deposited overlying the titanium layer. A titanium nitride capping layer is deposited over the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. The substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

US Patent:

6729014, May 4, 2004

Filed:

Sep 17, 2001

Appl. No.:

09/953542

Inventors:

Charles C. Lin - San Jose CA
Cheng T. Horng - San Jose CA
Min Li - Fremont CA
Kochan Ju - Fremont CA

Assignee:

Headway Technologies, Inc. - Milpitas CA

International Classification:

G11B 5127

US Classification:

2960314

Abstract:

A method for forming a top spin-valve SyAP GMR read sensor having a novel conductive lead overlay configuration and the sensor so formed. The lead overlay electrically contacts the sensor at a position within the SyAP pinned layer, thus simultaneously assuring improved electrical contact and destroying the GMR properties of the sensor at the junction to improve the definition of the sensor track width.

US Patent:

6765264, Jul 20, 2004

Filed:

May 27, 2003

Appl. No.:

10/446246

Inventors:

Paul Chang - Saratoga CA
Geeng-Chuan Chern - Cupertino CA
Wayne Y. W. Hsueh - San Jose CA
Vladimir Rodov - Redondo Beach CA
Charles Lin - Fremont CA

Assignee:

Advanced Power Devices - San Jose CA

International Classification:

H01L 2976

US Classification:

257336, 257408

Abstract:

A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction sepcarating the channel region from the substrate of first conductivity type, In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

US Patent:

6776883, Aug 17, 2004

Filed:

Mar 19, 2002

Appl. No.:

10/100754

Inventors:

Kochan Ju - Fremont CA
You Feng Zheng - San Jose CA
Charles Lin - San Jose CA

Assignee:

Headway Technologies, Inc. - Milpitas CA

International Classification:

B05D 512

US Classification:

20419234, 216 13, 216 22, 216 58, 427123, 427125, 427129, 427130, 427131, 427132, 427259, 427265, 427272, 427282, 427533

Abstract:

A magnetic read head with reduced side reading characteristics is described. This design combines use of a current channeling layer (CCL) with stabilizing longitudinal bias layers whose magnetization direction is canted relative to that of the free layer easy axis and that of the pinned layer (of the GMR). This provides several advantages: First, the canting of the free layer at the side region results in a reduction of side reading by reducing magnetic sensitivity in that region. Second, the CCL leads to a narrow current flow profile at the side region, therefore producing a narrow track width definition. A process for making this device is described. Said process allows some of the requirements for interface cleaning associated with prior art processes to be relaxed.

US Patent:

6821717, Nov 23, 2004

Filed:

Aug 2, 2002

Appl. No.:

10/210955

Inventors:

Charles C. Lin - San Jose CA
Kochan Ju - Fremont CA

Assignee:

Headway Technologies, Inc. - Milpitas CA

International Classification:

G11B 531

US Classification:

430320, 430314, 430319, 2960307

Abstract:

As the recording density of magnetic disk drives approaches 100 Gbits/in , write track lengths of about 0. 10 microns will be required. This cannot be accomplished using conventional photolithography. The present invention solves this problem by first forming on the bottom pole of the write head a cavity in a layer of photoresist, using conventional means. A seed layer of non-magnetic material is electrolessly laid down, following which a second layer of photoresist is deposited and patterned to form a second cavity that symmetrically surrounds the first one, thereby forming a mold around it. Ferromagnetic metal is then electro-deposited in this mold to form the top magnetic pole. Following the removal of all photoresist and a brief selective etch of the bottom pole, an extremely narrow write head is obtained.

US Patent:

6913946, Jul 5, 2005

Filed:

Jun 13, 2003

Appl. No.:

10/461236

Inventors:

Charles Lin - Fremont CA, US

Assignee:

Aptos Corporation - Milpitas CA

International Classification:

H01L021/44
H01L021/48
H01L021/50

US Classification:

438106, 438112, 438124, 438126, 438411, 438421, 438422, 438619, 438624, 438637, 438902, 438958, 438976

Abstract:

A method of making a semiconductor device comprising: providing a semiconductor substrate having a plurality of discrete devices formed therein, and a plurality of metal layers and support layers, the support layers comprising an uppermost support layer and other support layers, and wherein each metal layer has an associated support layer having at least a portion underlying the metal layer, and wherein the plurality of metal layers includes an uppermost metal layer including a sealing pad having an opening therethrough, and a passivation layer having at least one opening therein exposing a portion of the sealing pad including the opening therethrough, and the uppermost support layer having a portion exposed through the opening in the sealing pad; exposing the uppermost support layer to an etching material through the opening in the sealing pad and etching away the support layers; and sealing the opening in the sealing pad.