Charles A May

US Patent:

6348413, Feb 19, 2002

Filed:

Sep 21, 1998

Appl. No.:

09/157855

Inventors:

Timothy Z. Hossain - Austin TX
Charles E. May - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

438682, 438680, 438683, 257770, 257773

Abstract:

In one aspect of the present invention, a method of forming a layer of silicide on a surface of a silicon-containing structure surface that is separated from a first structure by a second structure is provided. The method includes the steps of forming a layer of silicide-forming material on the surface of the silicon-containing structure, and the first and second structures. The layer of silicide-forming material is annealed in an ambient containing a nitrogen bearing species at a pressure greater than about one atmosphere to form the layer of silicide on the surface of the silicon-containing structure. The nitrogen bearing species reacts with the silicide-forming material to retard the formation of silicide on the third structure. The method reduces the potential for silicide bridging between, for example, the gate and source/drain regions of a transistor during silicide contact formation.

US Patent:

6362510, Mar 26, 2002

Filed:

Dec 7, 1998

Appl. No.:

09/206550

Inventors:

Mark I. Gardner - Cedar Creek TX
Charles E. May - Gresham OR

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257374, 257602, 257610, 257647

Abstract:

A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surface of the dielectric layer. A silicon epitaxial layer is then grown within the groove. Barrier atoms are incorporated into the silicon epitaxial layer concurrently with the epitaxial growth process.

US Patent:

6403445, Jun 11, 2002

Filed:

Apr 6, 1999

Appl. No.:

09/286729

Inventors:

Mark I. Gardner - Cedar Creek TX
Frederick N. Hause - Austin TX
Charles E. May - Gresham OR

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21762

US Classification:

438424, 438221, 438432, 438764

Abstract:

An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the trench, such as TEOS, and results in less over-etching of the trench isolation region. The quality of the dielectric isolation is consequently improved, and in particular, less leakage current flows across the trench isolation region. Moreover, less leakage current flows from a subsequently formed local interconnect layer.

US Patent:

6410967, Jun 25, 2002

Filed:

Oct 15, 1998

Appl. No.:

09/173273

Inventors:

Frederick N. Hause - Austin TX
Mark I. Gardner - Cedar Creek TX
Charles E. May - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2972

US Classification:

257377, 257382, 257384, 257396, 257408, 257412, 257413

Abstract:

A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the metal layer not covered by the masking layer are removed. A gate dielectric layer is formed within the opening upon the semiconductor substrate; in an embodiment, spacers are also formed upon opposed sidewall surfaces of the masking layer. A conductive material is then deposited upon the dielectric material to form a gate conductor. The masking material is then removed, source and drain and lightly doped drain impurity areas are formed in the semiconductor substrate, and the metal layer is annealed to form a silicide in close proximity to the channel region. By depositing the metal layer prior to forming the gate conductor, the process described herein allows formation of a metal silicide adjacent or in close proximity to the channel region of the transistor. The process also allows formation of a metal gate conductor self-aligned with lightly doped drain or source-drain impurity areas.

US Patent:

6420220, Jul 16, 2002

Filed:

Apr 16, 1999

Appl. No.:

09/292913

Inventors:

Mark I. Gardner - Cedar Creek TX
H. Jim Fulford - Austin TX
Charles E. May - Gresham OR

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 2100

US Classification:

438151

Abstract:

A method is provided for fabricating a semiconductor device, the method including forming a dielectric layer above a structure, forming a silicidable layer above the dielectric layer and forming a conductive layer above the silicidable layer. The method also includes forming a silicided layer by siliciding a portion of the conductive layer using at least a portion of the silicidable layer and forming a gate conductor having sides by patterning the silicided layer and the conductive layer.

US Patent:

6451657, Sep 17, 2002

Filed:

Feb 8, 2001

Appl. No.:

09/781044

Inventors:

Mark I. Gardner - Cedar Creek TX
Charles E. May - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438299, 438199, 438528, 438585

Abstract:

A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region.

US Patent:

6452412, Sep 17, 2002

Filed:

Mar 4, 1999

Appl. No.:

09/262238

Inventors:

Richard W. Jarvis - Austin TX
Iraj Emami - Austin TX
Charles E. May - Gresham OR

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G01R 3126

US Classification:

324765, 438 17

Abstract:

A drop-in test structure fabricated upon a production integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology are described. The test structure may be fabricated upon an integrated circuit elevational profile formed according to a subset of steps within a sequence of steps of the integrated circuit production methodology that culminates in a production integrated circuit intended for use by a consumer. According to an embodiment, the integrated circuit elevational profile may be fabricated according to a majority of the sequence of steps. Alternatively, the integrated circuit elevational profile may be fabricated according to a minority of the sequence of steps. The test structure may be fabricated upon die sites designated to receive the test structure. Alternatively, the test structure may be fabricated upon die sites otherwise intended for operable integrated circuits.

US Patent:

6531364, Mar 11, 2003

Filed:

Aug 5, 1998

Appl. No.:

09/129703

Inventors:

Mark I. Gardner - Cedar Creek TX
Charles E. May - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438287, 438591, 438775, 438783, 257324, 257411

Abstract:

A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.