Charles A Potter

US Patent:

7538405, May 26, 2009

Filed:

Jan 13, 2006

Appl. No.:

11/331267

Inventors:

Russell W. Gruhlke - San Jose CA, US
Charles E. Potter - Fort Collins CO, US

Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H01L 31/062
H01L 31/113
H01L 31/0232

US Classification:

257436, 257290

Abstract:

Surface plasmons are used to increase an energy absorbing efficiency of a semiconductor sensor.

US Patent:

7558641, Jul 7, 2009

Filed:

Mar 29, 2007

Appl. No.:

11/693708

Inventors:

Chung-Ho Huang - San Jose CA, US
Robert Hefty - Femont CA, US
Andrew Lui - Fremont CA, US
Dave Humbird - Oakland CA, US
Charles Potter - Eagle ID, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

G06F 19/00
G05B 13/02

US Classification:

700108, 700 49, 700104, 700121, 702 81, 715961

Abstract:

A computer-implemented method for performing recipe evaluation is provided. The computer-implemented method includes integrating a plurality of data sources into a single recipe report card framework. The recipe report card framework includes an editor for interacting with the plurality of data sources. The computer-implemented method also includes displaying a plurality of graphical displays. Each graphical display of the plurality of graphical displays is configured to present a signal parameter of a set of signal parameters for at least a substrate. The computer-implemented method further includes providing a plurality of criteria for each of the set of signal parameters. The computer-implemented method yet also includes providing a plurality of ranges for the each of the set of signal parameters. The computer-implemented method yet further includes providing an expert guide, which is configured to provide guidance in analyzing a recipe.

US Patent:

8394723, Mar 12, 2013

Filed:

Jan 7, 2010

Appl. No.:

12/684032

Inventors:

Juan Valdivia - Fremont CA, US
Shibu Gangadharan - Boise CA, US
Dave March - Eagle ID, US
Charles Potter - Eagle ID, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/3065
H01L 29/06

US Classification:

438710, 257618, 257E21218, 257E29022

Abstract:

A method for adjusting the geometry of photomask patterns is provided. Such adjusted pattern can be employed to achieve pattern doubling in subsequent layers. A patterned photoresist mask is provided over an underlayer. A polymer layer is placed over the mask. The mask is selectively trimmed to generate individual mask features having an increased aspect ratio. Subsequent pattern layers can be formed on the trimmed mask pattern to generate a hard mask having increased pattern density. The hard mask is selectively etched and the material of the trimmed mask pattern is removed. The underlayer is then etched to achieve pattern transfer from the hard mask to the underlayer to achieve a final double density pattern.

US Patent:

20170249191, Aug 31, 2017

Filed:

Feb 25, 2016

Appl. No.:

15/052946

Inventors:

- Amsterdam, NL
Hsing Heng Hsieh - San Jose CA, US
Charles Dominic Potter - San Jose CA, US

International Classification:

G06F 9/50

Abstract:

In some examples, a method includes assigning, to each respective task queue of a plurality of task queues, a respective priority ratio based at least in part on a number of tasks in the respective task queue. The method further includes assigning, by a processor of a plurality of processors, respective tasks from the respective task queues to at least one processor of the plurality of processors in an order based at least in part on the respective priority ratio, wherein the respective priority ratio defines a relative frequency with which tasks from the respective task queue are assigned to the at leak one processor.

US Patent:

20160098306, Apr 7, 2016

Filed:

Oct 1, 2014

Appl. No.:

14/504117

Inventors:

- Amsterdam, NL
Hsing H. Hsieh - San Jose CA, US
Charles D. Potter - San Jose CA, US

International Classification:

G06F 9/54
G06F 9/445

Abstract:

In general, techniques are described for performing hardware-based queue automation for hardware engines. An apparatus comprising a hardware engine and a hardware event queue manager may be configured to perform the techniques. The hardware event queue manager may be configured to receive, from a processing unit separate from the hardware event queue manager, an event to be processed by the hardware engine, and perform queue management with respect to an event queue to schedule processing of the event by the hardware engine.