Charles J Vaughn

US Patent:

48706655, Sep 26, 1989

Filed:

Aug 4, 1988

Appl. No.:

7/228159

Inventors:

Charles J. Vaughn - Fremont CA

Assignee:

GTE Government Systems Corporation - Stamford CT

International Classification:

H03K 504
H03K 5135

US Classification:

328 61

Abstract:

A technique for accurately controlling both the pulse repetition interval and pulse width of a pulse signal generator which uses a crystal oscillator to maintain a very accurate time base. Two separate digital counters clock-in the clock pulses. When the desired number of clock pulses are registered by the first counter, a first digital comparator generates a start pulse which resets the first counter and triggers an output flip-flop. The change of state in the flip-flop enables the second counter to begin its count. When the desired number of clock pulses are registered by the second counter, a second digital comparator generates an end pulse which resets the second counter and triggers the flip-flop a second time. The second change of state of the flip-flop disables the second counter until the first comparator generates a new start pulse. The new start pulse toggles the flip-flop and the entire process is repeated continuously to generate at the output of the flip-flop a periodic pulse train having the desired pulse width with the leading edges separated by the desired pulse repetition interval.

US Patent:

48810401, Nov 14, 1989

Filed:

Aug 4, 1988

Appl. No.:

7/228158

Inventors:

Charles J. Vaughn - Fremont CA

Assignee:

GTE Government Systems Corporation - Stamford CT

International Classification:

H03K 504
H03K 5135

US Classification:

328 61

Abstract:

The pulse signal generator produces a repetitive pulse output signal consisting of repetitive pulse groups which may have either constant pulse intervals or staggered pulse intervals. Each pulse in the group also has an adjustable pulse width and may be time referenced to a clock pulse signal. The pulse generator employs cascaded stages of individual pulse generators: one stage for each pulse in the group. The first stage generates the first pulse in each group of n pulses and additionally controls the pulse group repetition interval and the pulse width of each pulse. A first counter/comparator generates a first start-pulse, when it counts N. sub. 1 clock pulses. The start-pulse resets the first counter and triggers an output bistable (multivibrator) circuit, which initiates the leading edge of the first output pulse of the group. When N. sub. 2 clock pulses are registered by a second counter, its associated comparator generates an "end-pulse" to reset the second counter and trigger the bistable circuit a second time. The second change of state of the bistable circuit completes the first output pulse and also disables the second counter until another start-pulse retoggles the bistable circuit.