Charles E Wallace

US Patent:

7521157, Apr 21, 2009

Filed:

Feb 9, 2006

Appl. No.:

11/351084

Inventors:

Charles H. Wallace - Portland OR, US
Swaminathan Sivakumar - Portland OR, US
Shannon E. Daviess - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 1/00

US Classification:

430 5

Abstract:

Cross-shaped sub-resolution assist features may be utilized to print lithographic patterns in semiconductor fabrication processes. The crosses may be isolated structures or may be part of a grid arrangement. The main features, such as contacts, may be positioned on the mask so as to be intersected by the cross-shaped sub-resolution assist features. In some embodiments, the cross-shaped sub-resolution assist features may intersect the main feature at its center point in both the x and y directions.

US Patent:

7569310, Aug 4, 2009

Filed:

Dec 7, 2005

Appl. No.:

11/296983

Inventors:

Charles H. Wallace - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 1/00
H01L 21/00
G06F 17/50

US Classification:

430 5, 430311, 716 20, 716 21

Abstract:

Sub-resolution assist features with trim ends are described for use in photolithography. A photolithography mask with elongated features is synthesized. A sub-resolution assist feature is applied to an end-to-end gap between the elongated features. Trim is applied to the ends of the sub-resolution assist feature, the trim connecting the sub-resolution assist feature to an end of a main feature, the trim having a narrower width than the remaining portion of the sub-resolution assist feature and the synthesized photolithography mask is modified to include the sub-resolution assist feature and trim.

US Patent:

7572557, Aug 11, 2009

Filed:

Dec 7, 2005

Appl. No.:

11/297209

Inventors:

Charles H. Wallace - Portland OR, US
Shannon E. Daviess - Hillsboro OR, US
Swaminathan Sivakumar - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 1/00
H01L 21/00
G06F 17/50

US Classification:

430 5, 430311, 716 20, 716 21

Abstract:

Sub-resolution assist features for non-collinear features are described for use in photolithography. A photolithography mask with elongated features is synthesized. An end-to-end gap between two features if found for which the ends of the two features facing the gap are linearly offset from one another. A sub-resolution assist feature is applied to the end-to-end gap between the elongated features, and the synthesized photolithography mask is modified to include the sub-resolution assist feature.

US Patent:

7632610, Dec 15, 2009

Filed:

Sep 2, 2004

Appl. No.:

10/933625

Inventors:

Charles H. Wallace - Portland OR, US
Paul A. Nyhus - Portland OR, US
Swaminathan (Sam) Sivakumar - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 1/00

US Classification:

430 5, 716 19, 716 21

Abstract:

Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature.

US Patent:

7648803, Jan 19, 2010

Filed:

Mar 27, 2006

Appl. No.:

11/390779

Inventors:

Sam Sivakumar - Portland OR, US
Charles H. Wallace - Portland OR, US
Shannon E. Daviess - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 1/00
G06F 17/50

US Classification:

430 5, 716 21

Abstract:

Diagonal corner-to-corner sub-resolution assist features for use in photolithography are described. The diagonal features may be applied to one or a group of main features. Such features may be developed starting by synthesizing a photolithography mask having a first feature aligned along a linear axis and having a corner and a second feature aligned along a linear axis and having a corner, the corners of first and second features being separated from each other by a gap. The features may be developed by determining at least one diagonal line between the corners of the features to bridge the gap between the corners, applying a sub-resolution assist feature along the determined line, and modifying the synthesized photolithography mask to include the sub-resolution assist feature.

US Patent:

7709866, May 4, 2010

Filed:

Jun 26, 2007

Appl. No.:

11/821971

Inventors:

Nadia Rahhal-Orabi - Hillsboro OR, US
Charles H. Wallace - Portland OR, US
Alison Davis - Hillsboro OR, US
Swaminathan Sivakumar - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/51
H01L 21/469

US Classification:

257288, 257752, 257750, 257E23186, 438792

Abstract:

In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.

US Patent:

7759028, Jul 20, 2010

Filed:

Nov 23, 2009

Appl. No.:

12/623615

Inventors:

Charles H. Wallace - Portland OR, US
Swaminathan Sam Sivakumar - Portland OR, US
Paul A. Nyhus - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 1/00

US Classification:

430 5

Abstract:

Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature.

US Patent:

7820550, Oct 26, 2010

Filed:

Sep 5, 2008

Appl. No.:

12/205744

Inventors:

Paul Nyhus - Portland OR, US
Charles Wallace - Portland OR, US
Swaminathan Sivakumar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/311

US Classification:

438694, 438725, 438781, 430312, 257E21236, 257E21259, 257E21492

Abstract:

A method of forming a pattern on a wafer is provided. The method includes applying a photoresist on the wafer and exposing the wafer to define a first pattern on the photoresist. The method also includes exposing the wafer to define a second pattern on the photoresist, wherein each of the first and second patterns comprises unexposed portions of the photoresist and developing the wafer to form the first and second patterns on the photoresist, wherein the first and second patterns are formed by removing the unexposed portions of the photoresist.