Charles T Wallace

US Patent:

20220415736, Dec 29, 2022

Filed:

Jun 23, 2021

Appl. No.:

17/356036

Inventors:

- Santa Clara CA, US
Shashi VYAS - Euclid OH, US
Andy Chih-Hung WEI - Yamhill OR, US
Charles H. WALLACE - Portland OR, US

International Classification:

H01L 23/29
H01L 27/088
H01L 29/78
H01L 29/66
H01L 23/31
H01L 21/56
H01L 21/8234
H01L 29/49
H01L 29/51

Abstract:

Embodiments described herein may be related to apparatuses, processes, and techniques related to protecting metal gates within transistor gate structures during SAC patterning. In particular, embodiments include area selective deposition techniques to deposit films on the gate or on a gate cap that have a good selectivity to SAC etch. In embodiments the film may include a combination of zirconium and/or oxygen, or may include zirconium oxide. Other embodiments may be described and/or claimed.