Chetan D Hiremath

US Patent:

7340538, Mar 4, 2008

Filed:

Dec 3, 2003

Appl. No.:

10/727277

Inventors:

Kuriappan P. Alappat - Portland OR, US
Chetan Hiremath - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00
G06F 5/00

US Classification:

710 5, 710 6, 710 41, 709224, 709226, 718104

Abstract:

A method for dynamic assignment of slot-dependent static network port addresses. Under the method, a slot address and shelf address are determined for a card modular platform board installed in a given slot in a shelf. The slot and shelf addresses are used as inputs to return a unique network address. The unique network address is then assigned as a static network address for the board's network port. The unique address may be provided by an address proxy, including a boot server. Firmware and/or software stored on a board may also be employed to obtain the static network address. The address may be obtained from a pre-configured lookup table, or dynamically determined using an algorithm.

US Patent:

7424396, Sep 9, 2008

Filed:

Sep 26, 2005

Appl. No.:

11/235467

Inventors:

Rakesh Dodeja - Portland OR, US
Neelam Chandwani - Portland OR, US
Chetan Hiremath - Portland OH, US
Wen Wei - Beaverton OR, US
Udayan Mukherjee - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 19/00

US Classification:

702185, 714 25

Abstract:

Faults are monitored with information from agents for a plurality of sensors located on a plurality of circuit boards. A policy containing a error event thresholds against which the stored sensor information can be compared. Actions can be initiated by a fault module when one or more of the error event thresholds is exceeded.

US Patent:

7424666, Sep 9, 2008

Filed:

Sep 26, 2005

Appl. No.:

11/234995

Inventors:

Neelam Chandwani - Portland OR, US
Udayan Mukheriee - Portland OR, US
Santosh Balakrishnan - Gilbert AZ, US
Rakesh Dodeja - Portland OR, US
Chetan Hiremath - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00
H03M 13/00

US Classification:

714799

Abstract:

A fault module supports detection, analysis, and/or logging of various faults in a processor system. In one embodiment, the system is provided on a multi-core, single die device.

US Patent:

7558849, Jul 7, 2009

Filed:

Aug 10, 2005

Appl. No.:

11/201608

Inventors:

Neelam Chandwani - Portland OR, US
Udayan Mukherjee - Portland OR, US
Chetan Hiremath - Portland OR, US
Rakesh Dodeja - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/173
H02H 5/04
H05K 7/20
G06G 19/00
G06F 11/00

US Classification:

709223, 361103, 361688, 700130, 370219

Abstract:

A hardware management module is enabled to perform hardware management for a modular platform system that includes a plurality of modular platform shelves coupled via one or more communication links in a network. Hardware management to include monitoring board interfaces resident on one or more backplanes within the plurality of modular platform shelves, detecting when a board is received and coupled to a board interface and performing one or more hardware management functions to include obtaining field replaceable unit information from the detected board.

US Patent:

7702966, Apr 20, 2010

Filed:

Sep 7, 2005

Appl. No.:

11/220796

Inventors:

Neelam Chandwani - Portland OR, US
Udayan Mukherjee - Portland OR, US
Chetan Hiremath - Portland OR, US
Rakesh Dodeja - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/34

US Classification:

714 47, 714 38

Abstract:

A method for managing a system includes monitoring a plurality of applications running in the system for errors. A prediction is made as to whether errors detected would result in a failure. Fault recovery is initiated in response to a failure prediction. According to one aspect of the present invention, monitoring the plurality of applications includes reading error recorders associated with error occurrence. Other embodiments are described and claimed.

US Patent:

7752468, Jul 6, 2010

Filed:

Jun 6, 2006

Appl. No.:

11/447701

Inventors:

Rakesh Dodeja - Portland OR, US
Neelam Chandwani - Portland OR, US
Chetan Hiremath - Portland OR, US
Udayan Mukherjee - Portland OR, US
Anthony Ambrose - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713300, 713 1

Abstract:

A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.

US Patent:

7817394, Oct 19, 2010

Filed:

Jul 28, 2004

Appl. No.:

10/900927

Inventors:

Udayan Mukherjee - Portland OR, US
Chetan Hiremath - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H02H 5/04

US Classification:

361103, 700 22, 710100, 710305, 717121

Abstract:

A method according to one embodiment may include discovering, by software, at least one variable from at least one component populated on a shelf system. The method may also include performing, by the software, at least one shelf management function based on at least one variable. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

US Patent:

8412972, Apr 2, 2013

Filed:

Jun 28, 2010

Appl. No.:

12/824597

Inventors:

Kin-Hang Cheung - San Jose CA, US
Neelam Chandwani - Portland OR, US
Chetan D. Hiremath - Portland OR, US
Udayan Mukherjee - Portland OR, US
Rakesh Dodeja - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/30

US Classification:

713340, 713300

Abstract:

Described herein are a method and an apparatus for reducing power consumption of memories by monitoring the power states of the memories via an operating system. The method comprises reading counter values corresponding to power states of each memory of a plurality memories; computing a power state usage corresponding to the power states of each memory of the plurality, the computing based on the counter values; determining whether the power state usage exceeds a predetermined threshold usage; and adjusting current and future usage of each memory of the plurality in response to determining that the power state usage exceeds the predetermined threshold usage.