Chi Chung Chen

US Patent:

7180165, Feb 20, 2007

Filed:

Sep 5, 2003

Appl. No.:

10/656452

Inventors:

Mark Ellsberry - Santa Clara CA, US
Charles E. Schmitz - Granada Hills CA, US
Chi She Chen - Walnut CA, US
Victor Allison - Huntington TX, US

Assignee:

Sanmina, SCI Corporation - San Jose CA

International Classification:

H01L 23/02

US Classification:

257686, 257777, 257685, 257778, 438108, 438109, 361760

Abstract:

On implementation of the invention provides a stackable chip-scale package for improving memory density that may be mounted within a limited area or module. A novel staggered routing scheme enables the use of the same trace routing at every level of the stacked architecture for efficiently accessing individual memory devices in a chip-scale package stack. The use of a ball grid array chip-scale package architecture in combination with thermally compatible materials decreases the risk of thermal cracking while improving heat dissipation. Moreover, this architecture permits mounting support components, such as capacitors and resistors, on the chip-scale package.

US Patent:

RE42363, May 17, 2011

Filed:

Feb 15, 2010

Appl. No.:

12/557643

Inventors:

Mark Ellsberry - Santa Clara CA, US
Charles E. Schmitz - Granada Hills CA, US
Chi She Chen - Walnut CA, US
Victor Allison - Huntington TX, US
Jon Schmidt - San Juan Capistrano CA, US

Assignee:

Sanmina-SCI Corporation - San Jose CA

International Classification:

H01L 23/02

US Classification:

257686, 257777, 257685, 257778, 438108, 438109, 361760

Abstract:

On implementation of the invention provides a stackable chip-scale package for improving memory density that may be mounted within a limited area or module. A novel staggered routing scheme enables the use of the same trace routing at every level of the stacked architecture for efficiently accessing individual memory devices in a chip-scale package stack. The use of a ball grid array chip-scale package architecture in combination with thermally compatible materials decreases the risk of thermal cracking while improving heat dissipation. Moreover, this architecture permits mounting support components, such as capacitors and resistors, on the chip-scale package.

US Patent:

20180038275, Feb 8, 2018

Filed:

Mar 3, 2017

Appl. No.:

15/449685

Inventors:

Chi Keng Chen - Fremont CA, US

International Classification:

F02B 75/02

Abstract:

A method for improving the efficiency of an internal combustion engine having a cycle, for each cylinder of the engine, including intake, compression, power, and exhaust strokes, comprises inserting two strokes into the cycle in addition to the intake, compression, power, and exhaust strokes. No material other than air is introduced into each cylinder during either of the additional two strokes. A high efficiency internal combustion engine system having a cycle, for each cylinder of the engine, including intake, compression, power, and exhaust strokes, comprises a cylinder, a piston, an air intake device, a fuel injector, an exhaust valve device, a camshaft, and an electronic control unit (ECU) configured to control cylinder operation such that two strokes, in addition to the intake, compression, power, and exhaust strokes, are inserted into the cycle. No material other than air is introduced into each cylinder during either of the additional two strokes.