Chi W Lin

US Patent:

20200111836, Apr 9, 2020

Filed:

Oct 3, 2019

Appl. No.:

16/591944

Inventors:

- Taichung City, TW
Chi Shun LIN - Fremont CA, US

International Classification:

H01L 27/24
H01L 23/528
H01L 23/522
H01L 45/00
G11C 13/00

Abstract:

The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local bit line, source lines, and a shared bit line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local bit line extends in a column direction of the array area. The source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line. The shared bit line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.