Chi Jung Lin

US Patent:

54828198, Jan 9, 1996

Filed:

Apr 4, 1994

Appl. No.:

8/223255

Inventors:

Eddy Tjhia - Sunnyvale CA
Chi Lin - Milpitas CA
Anjali Anagol-Subbarao - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G03F 720

US Classification:

430394

Abstract:

A photolithographic process for forming a lead frame pattern or other pattern is described. In the preferred embodiment, a mask approximately 12 inches by 12 inches contains two nearly identical patterns: a first lead frame pattern is provided on one half of the mask, and a second lead frame pattern, having features reduced by 0. 3 mil, is provided on the other half of the mask. The first pattern is positioned over a copper web having a layer of photoresist laminated on it, and ultraviolet light is transmitted through the first pattern. The photoresist is thus exposed by a first image formed by the first pattern. While the copper web remains stationary, the mask is moved perpendicular to the length of the copper web so that the second pattern now forms a second image overlying the photoresist pattern from the first image. The photoresist layer is then exposed by the second image. The two nearly identical patterns on the mask essentially double expose the photoresist except for a 0.

US Patent:

20200111836, Apr 9, 2020

Filed:

Oct 3, 2019

Appl. No.:

16/591944

Inventors:

- Taichung City, TW
Chi Shun LIN - Fremont CA, US

International Classification:

H01L 27/24
H01L 23/528
H01L 23/522
H01L 45/00
G11C 13/00

Abstract:

The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local bit line, source lines, and a shared bit line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local bit line extends in a column direction of the array area. The source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line. The shared bit line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.