Chi Hung Lin

US Patent:

54596068, Oct 17, 1995

Filed:

May 10, 1993

Appl. No.:

8/058185

Inventors:

Lawrence Baranyai - Howell NJ
Francis H. Butler - Howell NJ
John C. Cox - Oakhurst NJ
Chi H. Lin - Holmdel NJ
Nattu V. Srinivasan - Eatontown NJ

Assignee:

AT&T IPM Corp. - Coral Gables FL

International Classification:

H04J 1400

US Classification:

359117

Abstract:

An upgrade arrangement wherein the switching functions of an in-service switch or cross-connect system are transferred or "re-homed" onto a new, larger capacity switch via the existing input and output ports of the original system. The re-homing can be performed without loss of service, even if the original system is operating at full-capacity. By exploiting the protection redundancy engineered into existing telecommunication switching systems, all of the signals being routed through the original switch are temporarily consolidated onto only one-half of the switching fabric normally required to accommodate such connectivity. This signal consolidation allows half of the original switch ports to be brought off-line (without a service disruption), and linked to the new, higher capacity switching fabric. The signals that had been consolidated within the original switching fabric are then re-routed onto the new switching fabric (via the linked ports), and the other half of the original switch ports are brought off-line and linked to the new switching fabric. The re-routed signals (still being switched in a consolidated format within the new switching fabric) are then redistributed (unconsolidated) among the linked ports and the new switching fabric so that a normal switching pattern is reestablished.

US Patent:

20200111836, Apr 9, 2020

Filed:

Oct 3, 2019

Appl. No.:

16/591944

Inventors:

- Taichung City, TW
Chi Shun LIN - Fremont CA, US

International Classification:

H01L 27/24
H01L 23/528
H01L 23/522
H01L 45/00
G11C 13/00

Abstract:

The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local bit line, source lines, and a shared bit line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local bit line extends in a column direction of the array area. The source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line. The shared bit line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.