Chi H Nguyen

Address:

1994 Plz Montez, San Jose, CA 95132

Phone:

4089426644

VIN:

2T2BK1BA9AC059338

Make:

LEXUS

Model:

RX 350

Year:

2010

Address:

1520 E Capitol Expy, San Jose, CA 95121

VIN:

19UUA76547A046544

Make:

ACURA

Model:

TL

Year:

2007

Address:

16020 49 St N, Clearwater, FL 33762

VIN:

5TDZK23C27S052613

Make:

TOYOTA

Model:

SIENNA

Year:

2007

Address:

3465 Suncrest Ave, San Jose, CA 95132

Phone:

4088393968

VIN:

WBANE735X7CM57248

Make:

BMW

Model:

5 SERIES

Year:

2007

US Patent:

7257750, Aug 14, 2007

Filed:

Jan 13, 2005

Appl. No.:

11/036630

Inventors:

Satwant Singh - Fremont CA, US
Chi Nguyen - San Jose CA, US
Ann Wu - San Jose CA, US
Ting Yew - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G01R 31/28
G06F 11/00

US Classification:

714732, 714736

Abstract:

In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

US Patent:

7401280, Jul 15, 2008

Filed:

May 18, 2007

Appl. No.:

11/750790

Inventors:

Satwant Singh - Fremont CA, US
Chi Nguyen - San Jose CA, US
Ann Wu - San Jose CA, US
Ting Yew - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G01R 31/28
G06F 11/00

US Classification:

714732, 714736

Abstract:

In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

US Patent:

7663401, Feb 16, 2010

Filed:

Nov 3, 2006

Appl. No.:

11/556528

Inventors:

Chi Minh Nguyen - San Jose CA, US
Chan-Chi Jason Cheng - Fremont CA, US
Timothy S. Swensen - Santa Clara CA, US
Giai Trinh - Milpitas CA, US
Yi Chiang - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/177

US Classification:

326 41, 326 38, 36523002, 36523003

Abstract:

A programmable logic device, in accordance with an embodiment of the present invention, includes a plurality of multiplexers, having fuse input terminals and input signal terminals, and a plurality of associated fuses providing fuse signals to the fuse input terminals to control selection of the input signal terminals. The fuses in a first state select a first input signal terminal of the input signal terminals, with a first multiplexer from the plurality of multiplexers receiving a first logic level signal at the first input signal terminal and providing the first logic level signal to the first input signal terminal of a first set of the plurality of multiplexers. The fuses associated with the first set are adapted to be programmed before the fuses associated with the first multiplexer.

US Patent:

7907461, Mar 15, 2011

Filed:

Mar 3, 2008

Appl. No.:

12/041614

Inventors:

Chi Minh Nguyen - San Jose CA, US
Martin L. Voogel - Los Altos CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G11C 7/02

US Classification:

365206, 365194, 365 76, 365154, 365 63

Abstract:

A method of preventing an unintentional state change in a data storage node of a latch is disclosed. The method comprises receiving a reference input signal; generating a delayed input signal based upon the reference clock signal; maintaining a state of a first data storage node of a plurality of data storage nodes by latching data at the first node using the reference input signal; and maintaining a state of a second data storage node of the plurality of data storage nodes by latching data at the second data storage node using the delayed input signal. A circuit for preventing an unintentional state change in a data storage node of a latch is also disclosed.

US Patent:

20100168511, Jul 1, 2010

Filed:

Sep 24, 2009

Appl. No.:

12/566556

Inventors:

Ketan P. Muni - San Jose CA, US
Hung V. Ha - San Jose CA, US
Chi Nguyen - Belmont CA, US
Randy S. Chan - San Jose CA, US
John Y. Chang - Mountain View CA, US

Assignee:

Acclarent, Inc. - Menlo Park CA

International Classification:

A61M 25/10
A61B 1/018
A61M 16/00

US Classification:

600104, 12820418, 604 9601

Abstract:

A method for dilating a stenotic region in an airway of a patient may include advancing a balloon catheter through the airway of the patient to position an inflatable balloon of the catheter within at least a portion of the stenotic region, maintaining a position of the catheter relative to the patient, and inflating the balloon of the catheter to dilate the stenotic region of the airway. A system for dilating a stenotic region in an airway of a patient may include a catheter shaft having an overall length of less than 70 cm, an inflatable balloon disposed along a distal portion of the catheter shaft, and a stylet.

US Patent:

20180214671, Aug 2, 2018

Filed:

Feb 5, 2018

Appl. No.:

15/888547

Inventors:

- Irvine CA, US
Hung V. Ha - San Jose CA, US
Chi Nguyen - Belmont CA, US
Randy S. Chan - San Jose CA, US
John Y. Chang - Los Altos CA, US

International Classification:

A61M 25/01
A61M 25/10
A61M 29/02
A61B 90/30
A61M 25/00

Abstract:

A method for dilating a stenotic region in an airway of a patient may include advancing a balloon catheter through the airway of the patient to position an inflatable balloon of the catheter within at least a portion of the stenotic region, maintaining a position of the catheter relative to the patient, and inflating the balloon of the catheter to dilate the stenotic region of the airway. A system for dilating a stenotic region in an airway of a patient may include a catheter shaft having an overall length of less than 70 cm, an inflatable balloon disposed along a distal portion of the catheter shaft, and a stylet.