Chien Chao Chen

Address:

4757 Parkwest Dr, San Jose, CA 95130

VIN:

2HGFG3B87CH503181

Make:

HONDA

Model:

CIVIC

Year:

2012

US Patent:

8084353, Dec 27, 2011

Filed:

Aug 10, 2007

Appl. No.:

11/891607

Inventors:

Chien Wei Chen - Santa Clara CA, US

Assignee:

Macronix International Co., Ltd. - Hsinchu

International Classification:

H01L 21/8242
H01L 21/4763
H01L 23/48

US Classification:

438622, 438253, 257225

Abstract:

Methods and apparatus for providing a memory array fabrication process that concurrently forms memory array elements and peripheral circuitry. The invention relates to a method for fabricating memory arrays using a process that concurrently forms memory array elements and peripheral circuitry and results in a reduction in pitch.

US Patent:

8248136, Aug 21, 2012

Filed:

Jan 17, 2011

Appl. No.:

13/007804

Inventors:

Fulong Zhang - Upper Macungie PA, US
Zheng Chen - Upper Macungie PA, US
Chien Kuang Chen - San Jose CA, US
John Schadt - Bethlehem PA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03H 11/26

US Classification:

327277, 327262, 327284

Abstract:

In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.

US Patent:

8461894, Jun 11, 2013

Filed:

Aug 14, 2012

Appl. No.:

13/585142

Inventors:

Fulong Zhang - Cupertino CA, US
Zheng Chen - Upper Macungie PA, US
Chien Kuang Chen - San Jose CA, US
John Schadt - Bethlehem PA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03H 11/26

US Classification:

327277, 327262, 327284

Abstract:

In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.

US Patent:

8575981, Nov 5, 2013

Filed:

Jun 29, 2012

Appl. No.:

13/538759

Inventors:

Chien Chen Chen - San Jose CA, US
YuanHeng Lo - San Jose CA, US
Pavan Kumar Alli - Sunnyvale CA, US
Minhui Yan - San Jose CA, US
Harmeet Bhugra - San Jose CA, US

Assignee:

Integrated Device Technology, Inc. - San Jose CA

International Classification:

H03L 7/06

US Classification:

327156, 327159, 375376

Abstract:

A frequency synthesizer is configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent frequency adjusting control signal. A temperature sensor is provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer. A control circuit is provided, which is configured to generate the temperature-dependent frequency adjusting control signal in response to the temperature measurement signal. This control circuit includes a cascaded arrangement of an oversampled data converter and a multi-stage digital filter, which is configured to generate a plurality of codes from respective ones of the digital filter stages, and a selection circuit, which is configured to use at least first and second ones of the plurality of codes in sequence during first and second consecutive time intervals to generate the temperature-dependent frequency adjusting control signal.

US Patent:

8604848, Dec 10, 2013

Filed:

Jun 29, 2012

Appl. No.:

13/538719

Inventors:

Chien Chen Chen - San Jose CA, US
Pavan Kumar Alli - Sunnyvale CA, US
Minhui Yan - San Jose CA, US
YuanHeng Lo - San Jose CA, US
Harmeet Bhugra - San Jose CA, US

Assignee:

Integrated Device Technology inc. - San Jose CA

International Classification:

H03L 7/06

US Classification:

327156, 327159, 375376

Abstract:

A frequency synthesizer includes a frequency generator configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent code. A temperature sensor is provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer. A control circuit is provided, which is configured to generate the temperature-dependent code in response to the temperature measurement signal and a plurality of clocks having unequal frequencies. The control circuit can include a cascaded arrangement of an oversampled data converter and a digital filter, which are sequentially responsive to first and second ones of the plurality of clocks during generation of the periodic output signal by the frequency generator.

US Patent:

20060059269, Mar 16, 2006

Filed:

Sep 13, 2004

Appl. No.:

10/939531

Inventors:

Chien Chen - Fremont CA, US
Richard Schober - Cupertino CA, US
Yolin Lih - San Jose CA, US
Ian Colloff - Los Gatos CA, US
Richard Reeve - San Mateo CA, US
Allen Lyu - Saratoga CA, US
Mohamed Talaat - San Jose CA, US

International Classification:

G06F 15/16

US Classification:

709235000, 709226000

Abstract:

An interconnect device for transmitting data packets includes a plurality of ports, a hub, and an arbiter. The hub is configured to connect the plurality of ports together. The arbiter is coupled to the hub for controlling transmission of data packets between the hub and the ports. A reset is provided in at least one of the ports. The reset is in communication with the arbiter such that arbiter can reset the port in response to a detected error in the port.

US Patent:

56873530, Nov 11, 1997

Filed:

Mar 3, 1995

Appl. No.:

8/397912

Inventors:

Chien Chen - Fremont CA
Yizhi Lu - Fremont CA

Assignee:

HaL Computer Systems, Inc. - Campbell CA

International Classification:

G06F 1204
G06F 1216

US Classification:

395482

Abstract:

A system and method providing ECC protection for all data block sizes for which a computer system supports store (ST) accesses includes an access control logic unit which converts store accesses for small data block (. ltoreq. 64-bits) into read-modify (merge)-write accesses and a data merge logic unit which merges 64-bit data blocks retrieved by the load access with the small data block of the store access to create a new 64-bit data block. The data merge logic unit utilizes a merge code provided from a look-up table in a programmable logic array to perform the merging of the data blocks. An ECC generation logic unit processes the merged 64-bit data block, including the new small data block.

US Patent:

20150343629, Dec 3, 2015

Filed:

Dec 31, 2013

Appl. No.:

14/655691

Inventors:

Barry WINGATE - San Jose CA, US
Chien Hsu CHEN - Millbrae CA, US

Assignee:

ZIRCON CORPORATION - Campbell CA

International Classification:

B25J 1/04
H05K 5/00
A45F 5/10

Abstract:

The present invention relates generally to a system, method, and apparatus for a handle coupled to a device. More specifically, aspects of the present invention relate to a handle releasably coupled to a device. Further still, aspects of the present invention relate to a handle releasably coupled to a hatch that is releasably coupled to a device. Further still, aspects of the present invention relate to a two-axis pivoting handle reliably and releasably coupled to a device. In still other aspects the present invention relates to a device coupled to a releasable handle via a releaseable hatch, and wherein the handle optionally having means for extending the handle. Optionally, the device has an electronic device secured thereto, and wherein the electronic device has at least one means to communicate with a computer device.