Chien Y Lee

US Patent:

6806513, Oct 19, 2004

Filed:

Oct 8, 2002

Appl. No.:

10/267342

Inventors:

Hin Fai Chau - Fremont CA
Clarence John Dunnrowicz - Santa Cruz CA
Yan Chen - Fremont CA
Chien Ping Lee - Fremont CA

Assignee:

EIC Corporation - Fremont CA

International Classification:

H01L 29737

US Classification:

257198, 257197

Abstract:

The safe operating area (SOA) in a heterojunction bipolar transistor is improved by inserting a material between the collector and subcollector of the transistor with the insertion layer being a material having a wider energy bandgap than the material of the collector. The insertion layer increases the breakdown field at the collector-subcollector junction and thereby increases the Kirk effect induced breakdown voltage.

US Patent:

7012288, Mar 14, 2006

Filed:

Oct 8, 2002

Appl. No.:

10/267215

Inventors:

Chien Ping Lee - Fremont CA, US
Hin Fai Chau - Fremont CA, US
Nanlei Larry Wang - Palo Alto CA, US
Clarence John Dunnrowicz - Santa Cruz CA, US
Yan Chen - Fremont CA, US
Barry Jia-Fu Lin - Cupertino CA, US

Assignee:

WJ Communications, Inc. - San Jose CA

International Classification:

H01L 31/0336

US Classification:

257197, 257198

Abstract:

The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (uniformly or stepped) doping between the base region and the underlying subcollector region with the collector doping being lower near the base and higher near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.

US Patent:

20040188712, Sep 30, 2004

Filed:

Apr 7, 2004

Appl. No.:

10/820343

Inventors:

Chien Ping Lee - Fremont CA, US
Frank Chau - Fremont CA, US
Nanlei Wang - Palo Alto CA, US
Clarence Dunnrowicz - Santa Cruz CA, US
Yan Chen - Fremont CA, US
Barry Lin - Cupertino CA, US

Assignee:

EiC Corporation - Fremont CA

International Classification:

H01L031/0328

US Classification:

257/197000, 257/198000

Abstract:

The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (continuous or stepped) doping between the base region and the underlying subcollector region with the collector doping being lowest near the base and highest near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.

US Patent:

20150166330, Jun 18, 2015

Filed:

Oct 6, 2014

Appl. No.:

14/507177

Inventors:

- San Jose CA, US
Chien Chen Lee - San Jose CA, US

International Classification:

B81B 7/00
B81C 1/00

Abstract:

A method for fabricating a MEMS-IC device structure can include receiving a CMOS substrate comprising a plurality of CMOS circuits and a surface portion. A MEMS substrate having at least one MEMS device can be received and coupled to the CMOS substrate. The MEMS substrate and the surface portion of the CMOS substrate can be encapsulated with a molding material, which forms a top surface. A first plurality of vias can be created in the molding material from the top surface to the surface portion of the CMOS substrate. A conductive material can be disposed within the first plurality of vias such that the conductive material is electrically coupled to a portion of the CMOS substrate. A plurality of interconnects can be formed from the conductive material to the top surface of the molding material and a plurality of solder balls can be formed upon these interconnects.