Chih Chieh Chen

US Patent:

7920431, Apr 5, 2011

Filed:

Jun 2, 2008

Appl. No.:

12/131152

Inventors:

Dean K. Nobunaga - Cupertino CA, US
June Lee - San Jose CA, US
Chih Liang Chen - Sunnyvale CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/22

US Classification:

36518914, 36518903, 36518916, 36518915, 36518917, 36518918, 36518919, 36523003, 36523005, 3652331, 36523319

Abstract:

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

US Patent:

8248868, Aug 21, 2012

Filed:

Apr 1, 2011

Appl. No.:

13/078563

Inventors:

Dean K. Nobunaga - Cupertino CA, US
June Lee - San Jose CA, US
Chih Liang Chen - Sunnyvale CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

36518914, 36518903, 36518916, 36518915, 36518917, 36518919, 36523003, 36523005, 3652331, 36523316, 36523317, 36523318, 36523319

Abstract:

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

US Patent:

8593889, Nov 26, 2013

Filed:

Aug 21, 2012

Appl. No.:

13/590849

Inventors:

Dean K. Nobunaga - Cupertino CA, US
June Lee - San Jose CA, US
Chih Liang Chen - Sunnyvale CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

36518914, 36518903, 36518916, 36518915, 36518917, 36518918, 36518919, 36523003, 36523005, 3652331, 36523316, 36523317, 36523318, 36523319

Abstract:

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

US Patent:

20200126601, Apr 23, 2020

Filed:

Oct 25, 2019

Appl. No.:

16/663958

Inventors:

- Boise ID, US
June Lee - San Jose CA, US
Chih Liang Chen - Sunnyvale CA, US

International Classification:

G11C 7/10
G11C 14/00
G11C 16/10
G11C 7/22
G06F 13/16

Abstract:

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

US Patent:

20180366166, Dec 20, 2018

Filed:

Aug 23, 2018

Appl. No.:

16/110294

Inventors:

- Boise ID, US
June Lee - San Jose CA, US
Chih Liang Chen - Sunnyvale CA, US

International Classification:

G11C 7/10
G11C 14/00
G11C 7/22
G11C 16/10
G06F 13/16

Abstract:

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

US Patent:

20170345468, Nov 30, 2017

Filed:

Aug 11, 2017

Appl. No.:

15/674586

Inventors:

- Boise ID, US
June Lee - San Jose CA, US
Chih Liang Chen - Sunnyvale CA, US

International Classification:

G11C 7/10
G06F 13/16
G11C 14/00
G11C 7/22
G11C 16/10

Abstract:

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

US Patent:

20160176014, Jun 23, 2016

Filed:

Feb 17, 2015

Appl. No.:

14/624197

Inventors:

- Santa Clara CA, US
Jeonghoon Oh - Saratoga CA, US
Chih Hung Chen - Sunnyvale CA, US
Samuel Hsu - Palo Alto CA, US
Gautam Dandavate - Sunnyvale CA, US

International Classification:

B24B 37/30
B24B 37/04

Abstract:

Embodiments of the present invention provide systems, apparatus, and methods for an improved polishing head including an upper portion and a lower portion, the lower portion adapted to hold a substrate and to tilt relative to the upper portion, the tilt enabled by a spherical bearing, wherein the lower portion is adapted to tilt while rotating the substrate against a rotating polishing pad so that the lower portion remains flush against the rotating polishing pad while resisting lateral friction force generated by the rotating polishing pad contacting the substrate and pushing the substrate laterally against the lower portion. Numerous additional aspects are disclosed.

US Patent:

20160064048, Mar 3, 2016

Filed:

Nov 11, 2015

Appl. No.:

14/938193

Inventors:

- Boise ID, US
June Lee - San Jose CA, US
Chih Liang Chen - Sunnyvale CA, US

International Classification:

G11C 7/10
G11C 14/00

Abstract:

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.