Caltech
Control Lead of Caltech Fsae Team
Pure Storage Jun 2016 - Sep 2016
Software Engineering Intern
Caltech Jun 2016 - Sep 2016
Teaching Assistant For Principles of Microprocessor System
Facebook Jun 2015 - Sep 2015
Internet.org Connectivity Lab Embedded Software Summer Intern
Caltech Jun 2014 - Sep 2014
Caltech Summer Undergraduate Research Fellowship
Education:
Caltech 2013 - 2017
Skills:
Python Matlab Nasm Assembly Embedded Software Chinese X86 Assembly Embedded Systems Pcb Layout Electrical Engineering C C++ Circuit Analysis Altium
An intervertebral locking device comprises one spiral elastic body, two bracing mounts and two sets of locking members. The two bracing mounts are fastened respectively to both ends of the spiral elastic body. The two sets of locking members are fastened respectively with the two bracing mounts such that each set of the locking members is anchored in one of the two vertebrae adjacent to a vertebra under treatment. The spiral elastic body and the vertebra under treatment evince similar elastic qualities, i. e. similar deflection characteristics. A plurality of bone grafts affinitive to the vertebra under treatment are deposited in the chambers of the spiral elastic body and in the spaces surrounding the spiral elastic body.
System-On-Chip, Mobile Terminal, And Method For Operating The System-On-Chip
- Suwon-si, KR Chih Jen LIN - Austin TX, US Jinook SONG - Seoul, KR Sungjae LEE - Seoul, KR Hyun-ki KOO - Seongnam-si, KR Donghyeon HAM - Seoul, KR
International Classification:
G06F 13/40 G06T 1/20 G06F 13/16
Abstract:
A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC includes a processor of the SoC including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus, the deadlock controller being configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and extract, via the second bus, state information of the isolated processor in the deadlock state.